Lines Matching refs:pll_rate
136 const u32 pll_rate[MAX_TUN_CLOCKS]; member
156 const u32 pll_rate[MAX_AXI_CLOCKS]; member
538 ulong pll_rate; in axi_clk_set() local
542 pll_rate = pll_get(sclk); in axi_clk_set()
557 if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate) in axi_clk_set()
558 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]); in axi_clk_set()
567 if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate) in axi_clk_set()
568 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]); in axi_clk_set()
576 ulong pll_rate; in tun_clk_set() local
580 pll_rate = pll_get(sclk); in tun_clk_set()
595 if (tun_clk_cfg.pll_rate[freq_idx] < pll_rate) in tun_clk_set()
596 ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]); in tun_clk_set()
605 if (tun_clk_cfg.pll_rate[freq_idx] >= pll_rate) in tun_clk_set()
606 ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]); in tun_clk_set()