Lines Matching refs:pllcfgr

156 	writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */  in configure_clocks()
171 	setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */  in configure_clocks()
172 	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,  in configure_clocks()
174 	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,  in configure_clocks()
176 	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,  in configure_clocks()
178 	clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,  in configure_clocks()
280 	pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);  in stm32_clk_get_pllsai_vco_rate()
405 		pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);  in stm32_clk_get_rate()
406 		plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)  in stm32_clk_get_rate()
408 		pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)  in stm32_clk_get_rate()
410 		pllq = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)  in stm32_clk_get_rate()