Lines Matching refs:clk_ctrl
101 static enum zynq_clk zynq_clk_get_cpu_pll(u32 clk_ctrl) in zynq_clk_get_cpu_pll() argument
103 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; in zynq_clk_get_cpu_pll()
116 static enum zynq_clk zynq_clk_get_peripheral_pll(u32 clk_ctrl) in zynq_clk_get_peripheral_pll() argument
118 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; in zynq_clk_get_peripheral_pll()
133 u32 clk_ctrl, reset, pwrdwn, mul, bypass; in zynq_clk_get_pll_rate() local
135 clk_ctrl = readl(zynq_clk_get_register(id)); in zynq_clk_get_pll_rate()
137 reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT; in zynq_clk_get_pll_rate()
138 pwrdwn = (clk_ctrl & PLLCTRL_PWRDWN_MASK) >> PLLCTRL_PWRDWN_SHIFT; in zynq_clk_get_pll_rate()
142 bypass = clk_ctrl & PLLCTRL_BPFORCE_MASK; in zynq_clk_get_pll_rate()
146 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; in zynq_clk_get_pll_rate()
154 u32 clk_ctrl, srcsel; in zynq_clk_get_gem_rclk() local
157 clk_ctrl = readl(&slcr_base->gem0_rclk_ctrl); in zynq_clk_get_gem_rclk()
159 clk_ctrl = readl(&slcr_base->gem1_rclk_ctrl); in zynq_clk_get_gem_rclk()
161 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; in zynq_clk_get_gem_rclk()
171 u32 clk_621, clk_ctrl, div; in zynq_clk_get_cpu_rate() local
174 clk_ctrl = readl(&slcr_base->arm_clk_ctrl); in zynq_clk_get_cpu_rate()
176 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_cpu_rate()
195 pll = zynq_clk_get_cpu_pll(clk_ctrl); in zynq_clk_get_cpu_rate()
203 u32 clk_ctrl, div; in zynq_clk_get_ddr2x_rate() local
205 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); in zynq_clk_get_ddr2x_rate()
207 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT; in zynq_clk_get_ddr2x_rate()
215 u32 clk_ctrl, div; in zynq_clk_get_ddr3x_rate() local
217 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); in zynq_clk_get_ddr3x_rate()
219 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT; in zynq_clk_get_ddr3x_rate()
227 u32 clk_ctrl, div0, div1; in zynq_clk_get_dci_rate() local
229 clk_ctrl = readl(&slcr_base->dci_clk_ctrl); in zynq_clk_get_dci_rate()
231 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_dci_rate()
232 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; in zynq_clk_get_dci_rate()
243 u32 clk_ctrl, div0; in zynq_clk_get_peripheral_rate() local
246 clk_ctrl = readl(zynq_clk_get_register(id)); in zynq_clk_get_peripheral_rate()
248 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_peripheral_rate()
254 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; in zynq_clk_get_peripheral_rate()
260 pll = zynq_clk_get_peripheral_pll(clk_ctrl); in zynq_clk_get_peripheral_rate()
318 u32 clk_ctrl, div0 = 0, div1 = 0; in zynq_clk_set_peripheral_rate() local
323 clk_ctrl = readl(reg); in zynq_clk_set_peripheral_rate()
325 pll = zynq_clk_get_peripheral_pll(clk_ctrl); in zynq_clk_set_peripheral_rate()
327 clk_ctrl &= ~CLK_CTRL_DIV0_MASK; in zynq_clk_set_peripheral_rate()
329 clk_ctrl &= ~CLK_CTRL_DIV1_MASK; in zynq_clk_set_peripheral_rate()
332 clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT; in zynq_clk_set_peripheral_rate()
339 clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT; in zynq_clk_set_peripheral_rate()
342 writel(clk_ctrl, reg); in zynq_clk_set_peripheral_rate()