Lines Matching refs:div1
227 u32 clk_ctrl, div0, div1; in zynq_clk_get_dci_rate() local
232 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; in zynq_clk_get_dci_rate()
235 zynq_clk_get_pll_rate(priv, ddrpll_clk), div0), div1); in zynq_clk_get_dci_rate()
244 u32 div1 = 1; in zynq_clk_get_peripheral_rate() local
254 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; in zynq_clk_get_peripheral_rate()
255 if (!div1) in zynq_clk_get_peripheral_rate()
256 div1 = 1; in zynq_clk_get_peripheral_rate()
266 div1); in zynq_clk_get_peripheral_rate()
289 u32 *div0, u32 *div1) in zynq_clk_calc_peripheral_two_divs() argument
303 *div1 = d1; in zynq_clk_calc_peripheral_two_divs()
318 u32 clk_ctrl, div0 = 0, div1 = 0; in zynq_clk_set_peripheral_rate() local
331 &div0, &div1); in zynq_clk_set_peripheral_rate()
332 clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT; in zynq_clk_set_peripheral_rate()