244 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)  in zynqmp_clk_get_cpu_pll()  argument
246 	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>  in zynqmp_clk_get_cpu_pll()
260 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)  in zynqmp_clk_get_ddr_pll()  argument
262 	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>  in zynqmp_clk_get_ddr_pll()
274 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)  in zynqmp_clk_get_peripheral_pll()  argument
276 	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>  in zynqmp_clk_get_peripheral_pll()
290 static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)  in zynqmp_clk_get_wdt_pll()  argument
292 	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>  in zynqmp_clk_get_wdt_pll()
306 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,  in zynqmp_clk_get_pll_src()  argument
313 		src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>  in zynqmp_clk_get_pll_src()
316 		src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>  in zynqmp_clk_get_pll_src()
337 	u32 clk_ctrl, reset, mul;  in zynqmp_clk_get_pll_rate()  local
341 	ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);  in zynqmp_clk_get_pll_rate()
347 	if (clk_ctrl & PLLCTRL_BYPASS_MASK)  in zynqmp_clk_get_pll_rate()
348 		freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);  in zynqmp_clk_get_pll_rate()
350 		freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);  in zynqmp_clk_get_pll_rate()
352 	reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;  in zynqmp_clk_get_pll_rate()
353 	if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))  in zynqmp_clk_get_pll_rate()
356 	mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;  in zynqmp_clk_get_pll_rate()
360 	if (clk_ctrl & (1 << 16))  in zynqmp_clk_get_pll_rate()
369 	u32 clk_ctrl, div;  in zynqmp_clk_get_cpu_rate()  local
374 	ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);  in zynqmp_clk_get_cpu_rate()
380 	div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;  in zynqmp_clk_get_cpu_rate()
382 	pll = zynqmp_clk_get_cpu_pll(clk_ctrl);  in zynqmp_clk_get_cpu_rate()
392 	u32 clk_ctrl, div;  in zynqmp_clk_get_ddr_rate()  local
397 	ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);  in zynqmp_clk_get_ddr_rate()
403 	div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;  in zynqmp_clk_get_ddr_rate()
405 	pll = zynqmp_clk_get_ddr_pll(clk_ctrl);  in zynqmp_clk_get_ddr_rate()
417 	u32 clk_ctrl, div0;  in zynqmp_clk_get_peripheral_rate()  local
422 	ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);  in zynqmp_clk_get_peripheral_rate()
428 	div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;  in zynqmp_clk_get_peripheral_rate()
433 		div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;  in zynqmp_clk_get_peripheral_rate()
438 	pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);  in zynqmp_clk_get_peripheral_rate()
452 	u32 clk_ctrl, div0;  in zynqmp_clk_get_wdt_rate()  local
457 	ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);  in zynqmp_clk_get_wdt_rate()
463 	div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;  in zynqmp_clk_get_wdt_rate()
467 	pll = zynqmp_clk_get_wdt_pll(clk_ctrl);  in zynqmp_clk_get_wdt_rate()
469 		ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);  in zynqmp_clk_get_wdt_rate()
474 		div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;  in zynqmp_clk_get_wdt_rate()
522 	u32 clk_ctrl, div0 = 0, div1 = 0;  in zynqmp_clk_set_peripheral_rate()  local
529 	ret = zynqmp_mmio_read(reg, &clk_ctrl);  in zynqmp_clk_set_peripheral_rate()
535 	pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);  in zynqmp_clk_set_peripheral_rate()
540 	clk_ctrl &= ~CLK_CTRL_DIV0_MASK;  in zynqmp_clk_set_peripheral_rate()
542 		clk_ctrl &= ~CLK_CTRL_DIV1_MASK;  in zynqmp_clk_set_peripheral_rate()
545 		clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;  in zynqmp_clk_set_peripheral_rate()
552 	clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;  in zynqmp_clk_set_peripheral_rate()
557 	ret = zynqmp_mmio_write(reg, mask, clk_ctrl);  in zynqmp_clk_set_peripheral_rate()