41 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,  in rkclk_set_pll()  argument
45 	struct rk322x_pll *pll = &cru->pll[pll_id];  in rkclk_set_pll()
79 static void rkclk_init(struct rk322x_cru *cru)  in rkclk_init()  argument
86 	rk_clrsetreg(&cru->cru_mode_con,  in rkclk_init()
92 	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);  in rkclk_init()
93 	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);  in rkclk_init()
106 	rk_clrsetreg(&cru->cru_clksel_con[0],  in rkclk_init()
111 	rk_clrsetreg(&cru->cru_clksel_con[1],  in rkclk_init()
129 	rk_clrsetreg(&cru->cru_clksel_con[0],  in rkclk_init()
134 	rk_clrsetreg(&cru->cru_clksel_con[1],  in rkclk_init()
154 	rk_clrsetreg(&cru->cru_clksel_con[10],  in rkclk_init()
163 	rk_clrsetreg(&cru->cru_mode_con,  in rkclk_init()
170 static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,  in rkclk_pll_get_rate()  argument
176 	struct rk322x_pll *pll = &cru->pll[pll_id];  in rkclk_pll_get_rate()
188 	con = readl(&cru->cru_mode_con);  in rkclk_pll_get_rate()
210 static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,  in rockchip_mmc_get_clk()  argument
220 		con = readl(&cru->cru_clksel_con[11]);  in rockchip_mmc_get_clk()
222 		con = readl(&cru->cru_clksel_con[12]);  in rockchip_mmc_get_clk()
227 		con = readl(&cru->cru_clksel_con[11]);  in rockchip_mmc_get_clk()
239 static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)  in rk322x_mac_set_clk()  argument
247 	if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {  in rk322x_mac_set_clk()
251 		u32 con = readl(&cru->cru_clksel_con[5]);  in rk322x_mac_set_clk()
263 			rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,  in rk322x_mac_set_clk()
274 static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,  in rockchip_mmc_set_clk()  argument
296 		rk_clrsetreg(&cru->cru_clksel_con[11],  in rockchip_mmc_set_clk()
299 		rk_clrsetreg(&cru->cru_clksel_con[12],  in rockchip_mmc_set_clk()
305 		rk_clrsetreg(&cru->cru_clksel_con[11],  in rockchip_mmc_set_clk()
314 	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);  in rockchip_mmc_set_clk()
317 static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)  in rk322x_ddr_set_clk()  argument
338 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,  in rk322x_ddr_set_clk()
340 	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);  in rk322x_ddr_set_clk()
342 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,  in rk322x_ddr_set_clk()
352 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);  in rk322x_clk_get_rate()
355 		rate = rkclk_pll_get_rate(priv->cru, clk->id);  in rk322x_clk_get_rate()
361 		rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);  in rk322x_clk_get_rate()
375 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);  in rk322x_clk_set_rate()
381 		new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,  in rk322x_clk_set_rate()
385 		new_rate = rk322x_ddr_set_clk(priv->cru, rate);  in rk322x_clk_set_rate()
388 		new_rate = rk322x_mac_set_clk(priv->cru, rate);  in rk322x_clk_set_rate()
402 	struct rk322x_cru *cru = priv->cru;  in rk322x_gmac_set_parent()  local
410 		rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);  in rk322x_gmac_set_parent()
420 		rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));  in rk322x_gmac_set_parent()
431 	struct rk322x_cru *cru = priv->cru;  in rk322x_gmac_extclk_set_parent()  local
441 		rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);  in rk322x_gmac_extclk_set_parent()
445 		rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));  in rk322x_gmac_extclk_set_parent()
475 	priv->cru = dev_read_addr_ptr(dev);  in rk322x_clk_ofdata_to_platdata()
484 	rkclk_init(priv->cru);  in rk322x_clk_probe()