143 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,  in rkclk_set_pll()  argument
147 	struct rk3288_pll *pll = &cru->pll[pll_id];  in rkclk_set_pll()
174 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,  in rkclk_configure_ddr()  argument
204 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,  in rkclk_configure_ddr()
207 	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);  in rkclk_configure_ddr()
214 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,  in rkclk_configure_ddr()
297 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)  in rockchip_mac_set_clk()  argument
305 	if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) {  in rockchip_mac_set_clk()
309 		u32 con = readl(&cru->cru_clksel_con[21]);  in rockchip_mac_set_clk()
324 			rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK,  in rockchip_mac_set_clk()
335 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,  in rockchip_vop_set_clk()  argument
346 	rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,  in rockchip_vop_set_clk()
348 	rkclk_set_pll(cru, CLK_NEW, &npll_config);  in rockchip_vop_set_clk()
357 	rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,  in rockchip_vop_set_clk()
363 		rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,  in rockchip_vop_set_clk()
367 		rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,  in rockchip_vop_set_clk()
376 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)  in rkclk_init()  argument
383 	rk_clrsetreg(&cru->cru_mode_con,  in rkclk_init()
389 	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);  in rkclk_init()
390 	rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);  in rkclk_init()
412 	rk_clrsetreg(&cru->cru_clksel_con[1],  in rkclk_init()
435 	rk_clrsetreg(&cru->cru_clksel_con[10],  in rkclk_init()
444 	rk_clrsetreg(&cru->cru_mode_con,  in rkclk_init()
450 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)  in rk3288_clk_configure_cpu()  argument
453 	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,  in rk3288_clk_configure_cpu()
456 	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);  in rk3288_clk_configure_cpu()
468 	rk_clrsetreg(&cru->cru_clksel_con[0],  in rk3288_clk_configure_cpu()
479 	rk_clrsetreg(&cru->cru_clksel_con[37],  in rk3288_clk_configure_cpu()
487 	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,  in rk3288_clk_configure_cpu()
492 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,  in rkclk_pll_get_rate()  argument
498 	struct rk3288_pll *pll = &cru->pll[pll_id];  in rkclk_pll_get_rate()
505 	con = readl(&cru->cru_mode_con);  in rkclk_pll_get_rate()
525 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_mmc_get_clk()  argument
535 		con = readl(&cru->cru_clksel_con[12]);  in rockchip_mmc_get_clk()
541 		con = readl(&cru->cru_clksel_con[11]);  in rockchip_mmc_get_clk()
547 		con = readl(&cru->cru_clksel_con[12]);  in rockchip_mmc_get_clk()
559 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_mmc_set_clk()  argument
583 		rk_clrsetreg(&cru->cru_clksel_con[12],  in rockchip_mmc_set_clk()
590 		rk_clrsetreg(&cru->cru_clksel_con[11],  in rockchip_mmc_set_clk()
597 		rk_clrsetreg(&cru->cru_clksel_con[12],  in rockchip_mmc_set_clk()
606 	return rockchip_mmc_get_clk(cru, gclk_rate, periph);  in rockchip_mmc_set_clk()
609 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_spi_get_clk()  argument
617 		con = readl(&cru->cru_clksel_con[25]);  in rockchip_spi_get_clk()
622 		con = readl(&cru->cru_clksel_con[25]);  in rockchip_spi_get_clk()
627 		con = readl(&cru->cru_clksel_con[39]);  in rockchip_spi_get_clk()
639 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_spi_set_clk()  argument
649 		rk_clrsetreg(&cru->cru_clksel_con[25],  in rockchip_spi_set_clk()
655 		rk_clrsetreg(&cru->cru_clksel_con[25],  in rockchip_spi_set_clk()
661 		rk_clrsetreg(&cru->cru_clksel_con[39],  in rockchip_spi_set_clk()
670 	return rockchip_spi_get_clk(cru, gclk_rate, periph);  in rockchip_spi_set_clk()
673 static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)  in rockchip_saradc_get_clk()  argument
677 	val = readl(&cru->cru_clksel_con[24]);  in rockchip_saradc_get_clk()
684 static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)  in rockchip_saradc_set_clk()  argument
691 	rk_clrsetreg(&cru->cru_clksel_con[24],  in rockchip_saradc_set_clk()
695 	return rockchip_saradc_get_clk(cru);  in rockchip_saradc_set_clk()
703 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);  in rk3288_clk_get_rate()
706 		new_rate = rkclk_pll_get_rate(priv->cru, clk->id);  in rk3288_clk_get_rate()
714 		new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);  in rk3288_clk_get_rate()
719 		new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);  in rk3288_clk_get_rate()
731 		new_rate = rockchip_saradc_get_clk(priv->cru);  in rk3288_clk_get_rate()
743 	struct rk3288_cru *cru = priv->cru;  in rk3288_clk_set_rate()  local
746 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);  in rk3288_clk_set_rate()
752 		rk3288_clk_configure_cpu(priv->cru, priv->grf);  in rk3288_clk_set_rate()
756 		new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);  in rk3288_clk_set_rate()
764 		new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);  in rk3288_clk_set_rate()
769 		new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);  in rk3288_clk_set_rate()
773 		new_rate = rockchip_mac_set_clk(priv->cru, rate);  in rk3288_clk_set_rate()
777 		new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);  in rk3288_clk_set_rate()
781 		rk_setreg(&cru->cru_clksel_con[28], 1 << 15);  in rk3288_clk_set_rate()
784 		rk_setreg(&cru->cru_clksel_con[6], 1 << 15);  in rk3288_clk_set_rate()
786 		rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);  in rk3288_clk_set_rate()
799 			rk_clrsetreg(&cru->cru_clksel_con[31],  in rk3288_clk_set_rate()
804 			rk_clrsetreg(&cru->cru_clksel_con[31],  in rk3288_clk_set_rate()
814 		rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);  in rk3288_clk_set_rate()
817 		rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);  in rk3288_clk_set_rate()
819 		rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);  in rk3288_clk_set_rate()
824 		new_rate = rockchip_saradc_set_clk(priv->cru, rate);  in rk3288_clk_set_rate()
847 	struct rk3288_cru *cru = priv->cru;  in rk3288_gmac_set_parent()  local
858 		rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);  in rk3288_gmac_set_parent()
874 		rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK,  in rk3288_gmac_set_parent()
931 	priv->cru = dev_read_addr_ptr(dev);  in rk3288_clk_ofdata_to_platdata()
949 	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);  in rk3288_clk_probe()
961 		reg = readl(&priv->cru->cru_mode_con);  in rk3288_clk_probe()
968 		rkclk_init(priv->cru, priv->grf);  in rk3288_clk_probe()