525 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_mmc_get_clk()  argument
555 	src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;  in rockchip_mmc_get_clk()
559 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_mmc_set_clk()  argument
565 	debug("%s: gclk_rate=%u\n", __func__, gclk_rate);  in rockchip_mmc_set_clk()
567 	src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);  in rockchip_mmc_set_clk()
606 	return rockchip_mmc_get_clk(cru, gclk_rate, periph);  in rockchip_mmc_set_clk()
609 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_spi_get_clk()  argument
636 	return DIV_TO_RATE(gclk_rate, div);  in rockchip_spi_get_clk()
639 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_spi_set_clk()  argument
644 	debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);  in rockchip_spi_set_clk()
645 	src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;  in rockchip_spi_set_clk()
670 	return rockchip_spi_get_clk(cru, gclk_rate, periph);  in rockchip_spi_set_clk()
701 	ulong new_rate, gclk_rate;  in rk3288_clk_get_rate()  local
703 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);  in rk3288_clk_get_rate()
714 		new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);  in rk3288_clk_get_rate()
719 		new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);  in rk3288_clk_get_rate()
727 		return gclk_rate;  in rk3288_clk_get_rate()
744 	ulong new_rate, gclk_rate;  in rk3288_clk_set_rate()  local
746 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);  in rk3288_clk_set_rate()
764 		new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);  in rk3288_clk_set_rate()
769 		new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);  in rk3288_clk_set_rate()