Lines Matching refs:postdiv1
35 u32 postdiv1; member
47 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
295 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
299 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
322 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | in rkclk_set_pll()
337 u32 postdiv1, postdiv2 = 1; in pll_para_config() local
350 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); in pll_para_config()
351 if (postdiv1 > max_postdiv1) { in pll_para_config()
352 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
353 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_para_config()
356 vco_khz = freq_khz * postdiv1 * postdiv2; in pll_para_config()
365 div->postdiv1 = postdiv1; in pll_para_config()
779 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; in rk3399_ddr_set_clk()
783 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; in rk3399_ddr_set_clk()
787 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; in rk3399_ddr_set_clk()
791 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; in rk3399_ddr_set_clk()
795 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; in rk3399_ddr_set_clk()