Lines Matching refs:sdr_ctrl

29 static struct socfpga_sdr_ctrl *sdr_ctrl =  variable
114 writel(ruleno, &sdr_ctrl->prot_rule_rdwr); in sdram_set_rule()
126 writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr); in sdram_set_rule()
130 &sdr_ctrl->prot_rule_id); in sdram_set_rule()
135 &sdr_ctrl->prot_rule_data); in sdram_set_rule()
138 writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr); in sdram_set_rule()
141 writel(0, &sdr_ctrl->prot_rule_rdwr); in sdram_set_rule()
152 writel(ruleno, &sdr_ctrl->prot_rule_rdwr); in sdram_get_rule()
153 writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr); in sdram_get_rule()
156 addr = readl(&sdr_ctrl->prot_rule_addr); in sdram_get_rule()
161 id = readl(&sdr_ctrl->prot_rule_id); in sdram_get_rule()
166 data = readl(&sdr_ctrl->prot_rule_data); in sdram_get_rule()
181 writel(0x0, &sdr_ctrl->protport_default); in sdram_set_protection_config()
206 writel(0x3ff, &sdr_ctrl->protport_default); in sdram_set_protection_config()
215 readl(&sdr_ctrl->protport_default)); in sdram_dump_protection_config()
331 writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); in sdr_load_regs()
334 writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1); in sdr_load_regs()
337 writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2); in sdr_load_regs()
340 writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3); in sdr_load_regs()
343 writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4); in sdr_load_regs()
346 writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing); in sdr_load_regs()
349 writel(dram_addrw, &sdr_ctrl->dram_addrw); in sdr_load_regs()
352 writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width); in sdr_load_regs()
355 writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width); in sdr_load_regs()
358 writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq); in sdr_load_regs()
361 writel(cfg->dram_intr, &sdr_ctrl->dram_intr); in sdr_load_regs()
364 writel(cfg->static_cfg, &sdr_ctrl->static_cfg); in sdr_load_regs()
367 writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width); in sdr_load_regs()
370 writel(cfg->port_cfg, &sdr_ctrl->port_cfg); in sdr_load_regs()
373 writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg); in sdr_load_regs()
376 writel(cfg->mp_priority, &sdr_ctrl->mp_priority); in sdr_load_regs()
379 writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0); in sdr_load_regs()
380 writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1); in sdr_load_regs()
381 writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2); in sdr_load_regs()
382 writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3); in sdr_load_regs()
385 writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0); in sdr_load_regs()
386 writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1); in sdr_load_regs()
387 writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2); in sdr_load_regs()
388 writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3); in sdr_load_regs()
391 writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0); in sdr_load_regs()
392 writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1); in sdr_load_regs()
393 writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2); in sdr_load_regs()
396 writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0); in sdr_load_regs()
399 writel(cfg->cport_width, &sdr_ctrl->cport_width); in sdr_load_regs()
402 writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap); in sdr_load_regs()
405 writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap); in sdr_load_regs()
408 writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap); in sdr_load_regs()
411 writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap); in sdr_load_regs()
414 writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr); in sdr_load_regs()
417 writel(cfg->dram_odt, &sdr_ctrl->dram_odt); in sdr_load_regs()
420 writel(cfg->extratime1, &sdr_ctrl->extratime1); in sdr_load_regs()
446 ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst, in sdram_mmr_init_full()
454 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0); in sdram_mmr_init_full()
458 clrsetbits_le32(&sdr_ctrl->static_cfg, in sdram_mmr_init_full()
487 temp = readl(&sdr_ctrl->dram_addrw); in sdram_calculate_size()
521 width = readl(&sdr_ctrl->dram_if_width); in sdram_calculate_size()