150 			       const dimm_params_t *dimm_params)  in set_csn_config()  argument
171 		if (dimm_params[dimm_number].n_ranks > 0) {  in set_csn_config()
191 		if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \  in set_csn_config()
192 		    (dimm_number == 1 && dimm_params[1].n_ranks > 0))  in set_csn_config()
196 		if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \  in set_csn_config()
197 		   (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))  in set_csn_config()
201 		if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \  in set_csn_config()
202 		    (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \  in set_csn_config()
203 		    (dimm_number == 3 && dimm_params[3].n_ranks > 0))  in set_csn_config()
215 		ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;  in set_csn_config()
216 		bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;  in set_csn_config()
219 			= dimm_params[dimm_number].n_banks_per_sdram_device;  in set_csn_config()
222 		row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;  in set_csn_config()
223 		col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;  in set_csn_config()
264 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)  in avoid_odt_overlap()  argument
267 	if (dimm_params[0].n_ranks == 4)  in avoid_odt_overlap()
272 	if ((dimm_params[0].n_ranks == 2) &&  in avoid_odt_overlap()
273 		(dimm_params[1].n_ranks == 2))  in avoid_odt_overlap()
277 	if (dimm_params[0].n_ranks == 4)  in avoid_odt_overlap()
281 	if ((dimm_params[0].n_ranks != 0) &&  in avoid_odt_overlap()
282 	    (dimm_params[2].n_ranks != 0))  in avoid_odt_overlap()
297 				const dimm_params_t *dimm_params)  in set_timing_cfg_0()  argument
329 	switch (avoid_odt_overlap(dimm_params)) {  in set_timing_cfg_0()
391 	odt_overlap = avoid_odt_overlap(dimm_params);  in set_timing_cfg_0()
2120 			       const dimm_params_t *dimm_params)  in set_ddr_dq_mapping()  argument
2126 		if (dimm_params[i].n_ranks)  in set_ddr_dq_mapping()
2134 	ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |  in set_ddr_dq_mapping()
2135 			((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |  in set_ddr_dq_mapping()
2136 			((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |  in set_ddr_dq_mapping()
2137 			((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |  in set_ddr_dq_mapping()
2138 			((dimm_params[i].dq_mapping[4] & 0x3F) << 2);  in set_ddr_dq_mapping()
2140 	ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |  in set_ddr_dq_mapping()
2141 			((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |  in set_ddr_dq_mapping()
2142 			((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |  in set_ddr_dq_mapping()
2143 			((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |  in set_ddr_dq_mapping()
2144 			((dimm_params[i].dq_mapping[11] & 0x3F) << 2);  in set_ddr_dq_mapping()
2146 	ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |  in set_ddr_dq_mapping()
2147 			((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |  in set_ddr_dq_mapping()
2148 			((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |  in set_ddr_dq_mapping()
2149 			((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |  in set_ddr_dq_mapping()
2150 			((dimm_params[i].dq_mapping[16] & 0x3F) << 2);  in set_ddr_dq_mapping()
2153 	ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |  in set_ddr_dq_mapping()
2154 			((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |  in set_ddr_dq_mapping()
2156 			 (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |  in set_ddr_dq_mapping()
2157 			dimm_params[i].dq_mapping_ors;  in set_ddr_dq_mapping()
2351 			       const dimm_params_t *dimm_params,  in compute_fsl_memctl_config_regs()  argument
2433 			= dimm_params[dimm_number].rank_density >> dbw_cap_adj;  in compute_fsl_memctl_config_regs()
2435 		if (dimm_params[dimm_number].n_ranks == 0) {  in compute_fsl_memctl_config_regs()
2474 					sa = dimm_params[dimm_number].base_address +  in compute_fsl_memctl_config_regs()
2478 					sa = dimm_params[dimm_number].base_address;  in compute_fsl_memctl_config_regs()
2483 				if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {  in compute_fsl_memctl_config_regs()
2484 					sa = dimm_params[dimm_number].base_address;  in compute_fsl_memctl_config_regs()
2497 				if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {  in compute_fsl_memctl_config_regs()
2498 					sa = dimm_params[dimm_number].base_address;  in compute_fsl_memctl_config_regs()
2511 				sa = dimm_params[dimm_number].base_address;  in compute_fsl_memctl_config_regs()
2513 				if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {  in compute_fsl_memctl_config_regs()
2538 		set_csn_config(dimm_number, i, ddr, popts, dimm_params);  in compute_fsl_memctl_config_regs()
2552 	set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);  in compute_fsl_memctl_config_regs()
2594 	set_ddr_dq_mapping(ddr, dimm_params);  in compute_fsl_memctl_config_regs()