237 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,  in __step_assign_addresses()  argument
243 	unsigned int first_ctrl = pinfo->first_ctrl;  in __step_assign_addresses()
244 	unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;  in __step_assign_addresses()
255 		switch (pinfo->memctl_opts[i].data_bus_width) {  in __step_assign_addresses()
260 				if (!pinfo->dimm_params[i][j].n_ranks)  in __step_assign_addresses()
262 				dw = pinfo->dimm_params[i][j].primary_sdram_width;  in __step_assign_addresses()
277 				dw = pinfo->dimm_params[i][j].data_width;  in __step_assign_addresses()
278 				if (pinfo->dimm_params[i][j].n_ranks  in __step_assign_addresses()
306 	current_mem_base = pinfo->mem_base;  in __step_assign_addresses()
308 	if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {  in __step_assign_addresses()
309 		rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>  in __step_assign_addresses()
311 		switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &  in __step_assign_addresses()
328 			if (pinfo->memctl_opts[i].memctl_interleaving) {  in __step_assign_addresses()
329 				switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {  in __step_assign_addresses()
350 				pinfo->common_timing_params[i].base_address =  in __step_assign_addresses()
352 				pinfo->common_timing_params[i].total_mem =  in __step_assign_addresses()
361 				pinfo->common_timing_params[i].base_address =  in __step_assign_addresses()
365 						pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];  in __step_assign_addresses()
366 					pinfo->dimm_params[i][j].base_address =  in __step_assign_addresses()
373 				pinfo->common_timing_params[i].total_mem =  in __step_assign_addresses()
385 			pinfo->common_timing_params[i].base_address =  in __step_assign_addresses()
390 					pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];  in __step_assign_addresses()
391 				pinfo->dimm_params[i][j].base_address =  in __step_assign_addresses()
398 			pinfo->common_timing_params[i].total_mem =  in __step_assign_addresses()
410 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
414 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,  in fsl_ddr_compute()  argument
420 	unsigned int first_ctrl =  pinfo->first_ctrl;  in fsl_ddr_compute()
421 	unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;  in fsl_ddr_compute()
424 	__maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;  in fsl_ddr_compute()
426 	fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;  in fsl_ddr_compute()
427 	common_timing_params_t *timing_params = pinfo->common_timing_params;  in fsl_ddr_compute()
428 	if (pinfo->board_need_mem_reset)  in fsl_ddr_compute()
429 		assert_reset = pinfo->board_need_mem_reset();  in fsl_ddr_compute()
445 			fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,  in fsl_ddr_compute()
455 					&(pinfo->spd_installed_dimms[i][j]);  in fsl_ddr_compute()
457 					&(pinfo->dimm_params[i][j]);  in fsl_ddr_compute()
502 					&(pinfo->dimm_params[i][j]);  in fsl_ddr_compute()
518 				 pinfo->dimm_params[i],  in fsl_ddr_compute()
536 					&pinfo->memctl_opts[i],  in fsl_ddr_compute()
537 					pinfo->dimm_params[i], i);  in fsl_ddr_compute()
548 			if (pinfo->board_mem_reset) {  in fsl_ddr_compute()
550 				pinfo->board_mem_reset();  in fsl_ddr_compute()
558 		check_interleaving_options(pinfo);  in fsl_ddr_compute()
559 		total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);  in fsl_ddr_compute()
574 				 &pinfo->memctl_opts[i],  in fsl_ddr_compute()
576 				 pinfo->dimm_params[i],  in fsl_ddr_compute()
614 			    0xFFFFFFULL) - pinfo->mem_base;  in fsl_ddr_compute()
620 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)  in __fsl_ddr_sdram()  argument
629 	first_ctrl = pinfo->first_ctrl;  in __fsl_ddr_sdram()
630 	last_ctrl = first_ctrl + pinfo->num_ctrls - 1;  in __fsl_ddr_sdram()
635 		total_memory = fsl_ddr_interactive(pinfo, 0);  in __fsl_ddr_sdram()
637 		total_memory = fsl_ddr_interactive(pinfo, 1);  in __fsl_ddr_sdram()
640 		total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);  in __fsl_ddr_sdram()
643 	switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {  in __fsl_ddr_sdram()
648 			pinfo->memctl_opts[first_ctrl].  in __fsl_ddr_sdram()
665 	if (pinfo->board_need_mem_reset)  in __fsl_ddr_sdram()
666 		deassert_reset = pinfo->board_need_mem_reset();  in __fsl_ddr_sdram()
668 		if (pinfo->common_timing_params[i].all_dimms_registered)  in __fsl_ddr_sdram()
673 		if (pinfo->common_timing_params[i].ndimms_present == 0) {  in __fsl_ddr_sdram()
682 		fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,  in __fsl_ddr_sdram()
687 		if (pinfo->board_mem_de_reset) {  in __fsl_ddr_sdram()
689 			pinfo->board_mem_de_reset();  in __fsl_ddr_sdram()
695 			fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),  in __fsl_ddr_sdram()
707 		if (pinfo->memctl_opts[i].memctl_interleaving) {  in __fsl_ddr_sdram()
708 			switch (pinfo->memctl_opts[i].  in __fsl_ddr_sdram()
719 						&pinfo->common_timing_params[i],  in __fsl_ddr_sdram()
726 						&pinfo->common_timing_params[i],  in __fsl_ddr_sdram()
737 						&pinfo->common_timing_params[i],  in __fsl_ddr_sdram()
747 						&pinfo->common_timing_params[i],  in __fsl_ddr_sdram()
771 			fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],  in __fsl_ddr_sdram()