Lines Matching refs:GG82563_REG
2144 #define GG82563_REG(page, reg) \ macro
2150 GG82563_REG(0, 16) /* PHY Specific Control */
2152 GG82563_REG(0, 17) /* PHY Specific Status */
2154 GG82563_REG(0, 18) /* Interrupt Enable */
2156 GG82563_REG(0, 19) /* PHY Specific Status 2 */
2158 GG82563_REG(0, 21) /* Receive Error Counter */
2160 GG82563_REG(0, 22) /* Page Select */
2162 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2164 GG82563_REG(0, 29) /* Alternate Page Select */
2166 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
2169 GG82563_REG(2, 21) /* MAC Specific Control Register */
2171 GG82563_REG(2, 26) /* MAC Specific Control 2 */
2174 GG82563_REG(5, 26) /* DSP Distance */
2178 GG82563_REG(193, 16) /* Kumeran Mode Control */
2180 GG82563_REG(193, 17) /* Port Reset */
2182 GG82563_REG(193, 18) /* Revision ID */
2184 GG82563_REG(193, 19) /* Device ID */
2186 GG82563_REG(193, 20) /* Power Management Control */
2188 GG82563_REG(193, 25) /* Rate Adaptation Control */
2192 GG82563_REG(194, 16) /* FIFO's Control/Status */
2194 GG82563_REG(194, 17) /* Control */
2196 GG82563_REG(194, 18) /* Inband Control */
2198 GG82563_REG(194, 19) /* Diagnostic */
2200 GG82563_REG(194, 20) /* Acknowledge Timeouts */
2202 GG82563_REG(194, 21) /* Advertised Ability */
2204 GG82563_REG(194, 23) /* Link Partner Advertised Ability */
2206 GG82563_REG(194, 24) /* Advertised Next Page */
2208 GG82563_REG(194, 25) /* Link Partner Advertised Next page */
2210 GG82563_REG(194, 26) /* Misc. */