Lines Matching +full:- +full:- +full:port
8 * U-Boot version:
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
18 #include <dm/device-internal.h>
33 #include <asm-generic/gpio.h>
38 /* Some linux -> U-Boot compatibility stuff */
81 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) argument
82 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) argument
87 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) argument
108 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) argument
109 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) argument
110 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) argument
111 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) argument
112 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
113 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) argument
114 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) argument
115 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
128 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) argument
138 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) argument
141 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) argument
143 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) argument
248 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) argument
251 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) argument
260 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) argument
349 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) argument
359 /* Per-port registers */
405 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
406 * relative to port->base.
409 /* Port Mac Control0 */
415 /* Port Mac Control1 */
419 /* Port Interrupt Mask */
422 /* Port Mac Control3 */
427 /* Port Mac Control4 */
497 #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \ argument
498 (0x4 * (port)))
504 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
506 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
508 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
599 /* Maximum number of T-CONTs of PON port */
605 /* Maximum number of TXQs used by single port */
631 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
663 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
670 /* Port flags */
706 * - lookup ID - 4 bits
707 * - port ID - 1 byte
708 * - additional information - 1 byte
709 * - header data - 8 bytes
710 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
716 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
718 (((offs) * 2) - ((offs) % 2) + 2)
727 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
728 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
729 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
730 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
731 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
732 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
733 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
734 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
735 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
736 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
737 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
738 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
739 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
740 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
741 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
742 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
743 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
744 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
745 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
746 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
747 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
748 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
749 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
750 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
751 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
754 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
885 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
887 #define MVPP2_BM_SWF_LONG_POOL(port) 0 argument
921 /* List of pointers to port structures */
941 /* Maximum number of RXQs per port */
960 /* Index of the port from the "group of ports" complex point
969 /* Per-port registers' base address */
979 /* Per-CPU port control */
1007 /* Index of first port's physical RXQ */
1112 /* Per-CPU Tx queue control */
1147 /* Per-CPU control of physical Tx queues */
1166 /* RX queue number, in the range 0-31 for physical RXQs */
1187 /* ID of port to which physical RXQ is mapped */
1188 int port; member
1190 /* Port's logic RXQ number to which physical RXQ is mapped */
1237 /* Pool number in the range 0-7 */
1261 /* Number of RXQs used by single port */
1263 /* Number of TXQs used by single port */
1272 * U-Boot internal data, mostly uncached buffers for descriptors and data
1299 writel(data, priv->base + offset); in mvpp2_write()
1304 return readl(priv->base + offset); in mvpp2_read()
1307 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, in mvpp2_txdesc_dma_addr_set() argument
1311 if (port->priv->hw_version == MVPP21) { in mvpp2_txdesc_dma_addr_set()
1312 tx_desc->pp21.buf_dma_addr = dma_addr; in mvpp2_txdesc_dma_addr_set()
1316 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0); in mvpp2_txdesc_dma_addr_set()
1317 tx_desc->pp22.buf_dma_addr_ptp |= val; in mvpp2_txdesc_dma_addr_set()
1321 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, in mvpp2_txdesc_size_set() argument
1325 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_size_set()
1326 tx_desc->pp21.data_size = size; in mvpp2_txdesc_size_set()
1328 tx_desc->pp22.data_size = size; in mvpp2_txdesc_size_set()
1331 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, in mvpp2_txdesc_txq_set() argument
1335 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_txq_set()
1336 tx_desc->pp21.phys_txq = txq; in mvpp2_txdesc_txq_set()
1338 tx_desc->pp22.phys_txq = txq; in mvpp2_txdesc_txq_set()
1341 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, in mvpp2_txdesc_cmd_set() argument
1345 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_cmd_set()
1346 tx_desc->pp21.command = command; in mvpp2_txdesc_cmd_set()
1348 tx_desc->pp22.command = command; in mvpp2_txdesc_cmd_set()
1351 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port, in mvpp2_txdesc_offset_set() argument
1355 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_offset_set()
1356 tx_desc->pp21.packet_offset = offset; in mvpp2_txdesc_offset_set()
1358 tx_desc->pp22.packet_offset = offset; in mvpp2_txdesc_offset_set()
1361 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, in mvpp2_rxdesc_dma_addr_get() argument
1364 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_dma_addr_get()
1365 return rx_desc->pp21.buf_dma_addr; in mvpp2_rxdesc_dma_addr_get()
1367 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0); in mvpp2_rxdesc_dma_addr_get()
1370 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, in mvpp2_rxdesc_cookie_get() argument
1373 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_cookie_get()
1374 return rx_desc->pp21.buf_cookie; in mvpp2_rxdesc_cookie_get()
1376 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0); in mvpp2_rxdesc_cookie_get()
1379 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, in mvpp2_rxdesc_size_get() argument
1382 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_size_get()
1383 return rx_desc->pp21.data_size; in mvpp2_rxdesc_size_get()
1385 return rx_desc->pp22.data_size; in mvpp2_rxdesc_size_get()
1388 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, in mvpp2_rxdesc_status_get() argument
1391 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_status_get()
1392 return rx_desc->pp21.status; in mvpp2_rxdesc_status_get()
1394 return rx_desc->pp22.status; in mvpp2_rxdesc_status_get()
1399 txq_pcpu->txq_get_index++; in mvpp2_txq_inc_get()
1400 if (txq_pcpu->txq_get_index == txq_pcpu->size) in mvpp2_txq_inc_get()
1401 txq_pcpu->txq_get_index = 0; in mvpp2_txq_inc_get()
1404 /* Get number of physical egress port */
1405 static inline int mvpp2_egress_port(struct mvpp2_port *port) in mvpp2_egress_port() argument
1407 return MVPP2_MAX_TCONT + port->id; in mvpp2_egress_port()
1411 static inline int mvpp2_txq_phys(int port, int txq) in mvpp2_txq_phys() argument
1413 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; in mvpp2_txq_phys()
1423 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
1424 return -EINVAL; in mvpp2_prs_hw_write()
1427 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; in mvpp2_prs_hw_write()
1429 /* Write tcam index - indirect access */ in mvpp2_prs_hw_write()
1430 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1432 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); in mvpp2_prs_hw_write()
1434 /* Write sram index - indirect access */ in mvpp2_prs_hw_write()
1435 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1437 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1447 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_read()
1448 return -EINVAL; in mvpp2_prs_hw_read()
1450 /* Write tcam index - indirect access */ in mvpp2_prs_hw_read()
1451 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1453 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, in mvpp2_prs_hw_read()
1455 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) in mvpp2_prs_hw_read()
1459 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1461 /* Write sram index - indirect access */ in mvpp2_prs_hw_read()
1462 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1464 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1472 /* Write index - indirect access */ in mvpp2_prs_hw_inv()
1481 priv->prs_shadow[index].valid = true; in mvpp2_prs_shadow_set()
1482 priv->prs_shadow[index].lu = lu; in mvpp2_prs_shadow_set()
1489 priv->prs_shadow[index].ri_mask = ri_mask; in mvpp2_prs_shadow_ri_set()
1490 priv->prs_shadow[index].ri = ri; in mvpp2_prs_shadow_ri_set()
1498 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu; in mvpp2_prs_tcam_lu_set()
1499 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK; in mvpp2_prs_tcam_lu_set()
1502 /* Update mask for single port in tcam sw entry */
1504 unsigned int port, bool add) in mvpp2_prs_tcam_port_set() argument
1509 pe->tcam.byte[enable_off] &= ~(1 << port); in mvpp2_prs_tcam_port_set()
1511 pe->tcam.byte[enable_off] |= 1 << port; in mvpp2_prs_tcam_port_set()
1514 /* Update port map in tcam sw entry */
1521 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0; in mvpp2_prs_tcam_port_map_set()
1522 pe->tcam.byte[enable_off] &= ~port_mask; in mvpp2_prs_tcam_port_map_set()
1523 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_set()
1526 /* Obtain port map from tcam sw entry */
1531 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_get()
1539 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte; in mvpp2_prs_tcam_data_byte_set()
1540 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable; in mvpp2_prs_tcam_data_byte_set()
1548 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)]; in mvpp2_prs_tcam_data_byte_get()
1549 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)]; in mvpp2_prs_tcam_data_byte_get()
1564 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8)); in mvpp2_prs_sram_bits_set()
1571 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8)); in mvpp2_prs_sram_bits_clear()
1624 bits = (pe->sram.byte[ai_off] >> ai_shift) | in mvpp2_prs_sram_ai_get()
1625 (pe->sram.byte[ai_en_off] << (8 - ai_shift)); in mvpp2_prs_sram_ai_get()
1652 shift = 0 - shift; in mvpp2_prs_sram_shift_set()
1658 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = in mvpp2_prs_sram_shift_set()
1680 offset = 0 - offset; in mvpp2_prs_sram_offset_set()
1689 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1691 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); in mvpp2_prs_sram_offset_set()
1692 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1694 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); in mvpp2_prs_sram_offset_set()
1706 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1709 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); in mvpp2_prs_sram_offset_set()
1711 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1713 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); in mvpp2_prs_sram_offset_set()
1731 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) { in mvpp2_prs_flow_find()
1734 if (!priv->prs_shadow[tid].valid || in mvpp2_prs_flow_find()
1735 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS) in mvpp2_prs_flow_find()
1738 pe->index = tid; in mvpp2_prs_flow_find()
1761 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1; in mvpp2_prs_tcam_first_free()
1764 if (!priv->prs_shadow[tid].valid) in mvpp2_prs_tcam_first_free()
1768 return -EINVAL; in mvpp2_prs_tcam_first_free()
1772 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add) in mvpp2_prs_mac_drop_all_set() argument
1776 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) { in mvpp2_prs_mac_drop_all_set()
1777 /* Entry exist - update port only */ in mvpp2_prs_mac_drop_all_set()
1781 /* Entry doesn't exist - create new */ in mvpp2_prs_mac_drop_all_set()
1786 /* Non-promiscuous mode for all ports - DROP unknown packets */ in mvpp2_prs_mac_drop_all_set()
1800 /* Update port mask */ in mvpp2_prs_mac_drop_all_set()
1801 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
1806 /* Set port to promiscuous mode */
1807 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add) in mvpp2_prs_mac_promisc_set() argument
1811 /* Promiscuous mode - Accept unknown packets */ in mvpp2_prs_mac_promisc_set()
1813 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) { in mvpp2_prs_mac_promisc_set()
1814 /* Entry exist - update port only */ in mvpp2_prs_mac_promisc_set()
1818 /* Entry doesn't exist - create new */ in mvpp2_prs_mac_promisc_set()
1823 /* Continue - set next lookup */ in mvpp2_prs_mac_promisc_set()
1841 /* Update port mask */ in mvpp2_prs_mac_promisc_set()
1842 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
1848 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index, in mvpp2_prs_mac_multi_set() argument
1859 if (priv->prs_shadow[index].valid) { in mvpp2_prs_mac_multi_set()
1860 /* Entry exist - update port only */ in mvpp2_prs_mac_multi_set()
1864 /* Entry doesn't exist - create new */ in mvpp2_prs_mac_multi_set()
1869 /* Continue - set next lookup */ in mvpp2_prs_mac_multi_set()
1890 /* Update port mask */ in mvpp2_prs_mac_multi_set()
1891 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_multi_set()
1896 /* Parser per-port initialization */
1897 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first, in mvpp2_prs_hw_port_init() argument
1904 val &= ~MVPP2_PRS_PORT_LU_MASK(port); in mvpp2_prs_hw_port_init()
1905 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first); in mvpp2_prs_hw_port_init()
1908 /* Set maximum number of loops for packet received from port */ in mvpp2_prs_hw_port_init()
1909 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port)); in mvpp2_prs_hw_port_init()
1910 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port); in mvpp2_prs_hw_port_init()
1911 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max); in mvpp2_prs_hw_port_init()
1912 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); in mvpp2_prs_hw_port_init()
1917 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port)); in mvpp2_prs_hw_port_init()
1918 val &= ~MVPP2_PRS_INIT_OFF_MASK(port); in mvpp2_prs_hw_port_init()
1919 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset); in mvpp2_prs_hw_port_init()
1920 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); in mvpp2_prs_hw_port_init()
1927 int port; in mvpp2_prs_def_flow_init() local
1929 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_prs_def_flow_init()
1932 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
1938 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
1968 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1977 /* Non-promiscuous mode for all ports - DROP unknown packets */ in mvpp2_prs_mac_init()
1993 /* place holders only - no ports */ in mvpp2_prs_mac_init()
2026 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2027 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2056 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2057 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2088 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2089 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2125 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2126 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2155 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2156 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2186 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2187 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2192 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */ in mvpp2_prs_etype_init()
2212 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2213 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2245 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE, in mvpp2_prs_default_init()
2248 if (!priv->prs_shadow) in mvpp2_prs_default_init()
2249 return -ENOMEM; in mvpp2_prs_default_init()
2288 /* Find tcam entry with matched pair <MAC DA, port> */
2306 if (!priv->prs_shadow[tid].valid || in mvpp2_prs_mac_da_range_find()
2307 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) || in mvpp2_prs_mac_da_range_find()
2308 (priv->prs_shadow[tid].udf != udf_type)) in mvpp2_prs_mac_da_range_find()
2311 pe->index = tid; in mvpp2_prs_mac_da_range_find()
2325 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port, in mvpp2_prs_mac_da_accept() argument
2333 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */ in mvpp2_prs_mac_da_accept()
2334 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, in mvpp2_prs_mac_da_accept()
2346 if (priv->prs_shadow[tid].valid && in mvpp2_prs_mac_da_accept()
2347 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) && in mvpp2_prs_mac_da_accept()
2348 (priv->prs_shadow[tid].udf == in mvpp2_prs_mac_da_accept()
2354 tid - 1); in mvpp2_prs_mac_da_accept()
2360 return -1; in mvpp2_prs_mac_da_accept()
2362 pe->index = tid; in mvpp2_prs_mac_da_accept()
2368 /* Update port mask */ in mvpp2_prs_mac_da_accept()
2369 mvpp2_prs_tcam_port_set(pe, port, add); in mvpp2_prs_mac_da_accept()
2376 return -1; in mvpp2_prs_mac_da_accept()
2378 mvpp2_prs_hw_inv(priv, pe->index); in mvpp2_prs_mac_da_accept()
2379 priv->prs_shadow[pe->index].valid = false; in mvpp2_prs_mac_da_accept()
2384 /* Continue - set next lookup */ in mvpp2_prs_mac_da_accept()
2389 while (len--) in mvpp2_prs_mac_da_accept()
2397 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2405 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF; in mvpp2_prs_mac_da_accept()
2406 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2414 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da) in mvpp2_prs_update_mac_da() argument
2419 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr, in mvpp2_prs_update_mac_da()
2425 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true); in mvpp2_prs_update_mac_da()
2430 memcpy(port->dev_addr, da, ETH_ALEN); in mvpp2_prs_update_mac_da()
2435 /* Set prs flow for the port */
2436 static int mvpp2_prs_def_flow(struct mvpp2_port *port) in mvpp2_prs_def_flow() argument
2441 pe = mvpp2_prs_flow_find(port->priv, port->id); in mvpp2_prs_def_flow()
2446 tid = mvpp2_prs_tcam_first_free(port->priv, in mvpp2_prs_def_flow()
2454 return -ENOMEM; in mvpp2_prs_def_flow()
2457 pe->index = tid; in mvpp2_prs_def_flow()
2460 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
2464 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2467 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); in mvpp2_prs_def_flow()
2468 mvpp2_prs_hw_write(port->priv, pe); in mvpp2_prs_def_flow()
2480 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index); in mvpp2_cls_flow_write()
2481 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]); in mvpp2_cls_flow_write()
2482 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]); in mvpp2_cls_flow_write()
2483 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]); in mvpp2_cls_flow_write()
2492 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid; in mvpp2_cls_lookup_write()
2494 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data); in mvpp2_cls_lookup_write()
2526 static void mvpp2_cls_port_config(struct mvpp2_port *port) in mvpp2_cls_port_config() argument
2531 /* Set way for the port */ in mvpp2_cls_port_config()
2532 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); in mvpp2_cls_port_config()
2533 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); in mvpp2_cls_port_config()
2534 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); in mvpp2_cls_port_config()
2539 le.lkpid = port->id; in mvpp2_cls_port_config()
2545 le.data |= port->first_rxq; in mvpp2_cls_port_config()
2551 mvpp2_cls_lookup_write(port->priv, &le); in mvpp2_cls_port_config()
2555 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port) in mvpp2_cls_oversize_rxq_set() argument
2559 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), in mvpp2_cls_oversize_rxq_set()
2560 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK); in mvpp2_cls_oversize_rxq_set()
2562 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), in mvpp2_cls_oversize_rxq_set()
2563 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS)); in mvpp2_cls_oversize_rxq_set()
2565 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); in mvpp2_cls_oversize_rxq_set()
2566 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); in mvpp2_cls_oversize_rxq_set()
2567 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
2583 return -EINVAL; in mvpp2_bm_pool_create()
2585 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id]; in mvpp2_bm_pool_create()
2586 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id]; in mvpp2_bm_pool_create()
2587 if (!bm_pool->virt_addr) in mvpp2_bm_pool_create()
2588 return -ENOMEM; in mvpp2_bm_pool_create()
2590 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, in mvpp2_bm_pool_create()
2592 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", in mvpp2_bm_pool_create()
2593 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); in mvpp2_bm_pool_create()
2594 return -ENOMEM; in mvpp2_bm_pool_create()
2597 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), in mvpp2_bm_pool_create()
2598 lower_32_bits(bm_pool->dma_addr)); in mvpp2_bm_pool_create()
2599 if (priv->hw_version == MVPP22) in mvpp2_bm_pool_create()
2601 (upper_32_bits(bm_pool->dma_addr) & in mvpp2_bm_pool_create()
2603 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); in mvpp2_bm_pool_create()
2605 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); in mvpp2_bm_pool_create()
2607 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_create()
2609 bm_pool->type = MVPP2_BM_FREE; in mvpp2_bm_pool_create()
2610 bm_pool->size = size; in mvpp2_bm_pool_create()
2611 bm_pool->pkt_size = 0; in mvpp2_bm_pool_create()
2612 bm_pool->buf_num = 0; in mvpp2_bm_pool_create()
2624 bm_pool->buf_size = buf_size; in mvpp2_bm_pool_bufsize_set()
2627 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); in mvpp2_bm_pool_bufsize_set()
2636 for (i = 0; i < bm_pool->buf_num; i++) { in mvpp2_bm_bufs_free()
2638 mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); in mvpp2_bm_bufs_free()
2641 bm_pool->buf_num = 0; in mvpp2_bm_bufs_free()
2652 if (bm_pool->buf_num) { in mvpp2_bm_pool_destroy()
2653 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id); in mvpp2_bm_pool_destroy()
2657 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); in mvpp2_bm_pool_destroy()
2659 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_destroy()
2673 bm_pool = &priv->bm_pools[i]; in mvpp2_bm_pools_init()
2674 bm_pool->id = i; in mvpp2_bm_pools_init()
2683 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); in mvpp2_bm_pools_init()
2684 for (i = i - 1; i >= 0; i--) in mvpp2_bm_pools_init()
2685 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]); in mvpp2_bm_pools_init()
2701 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM, in mvpp2_bm_init()
2703 if (!priv->bm_pools) in mvpp2_bm_init()
2704 return -ENOMEM; in mvpp2_bm_init()
2713 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, in mvpp2_rxq_long_pool_set() argument
2720 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_long_pool_set()
2722 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_long_pool_set()
2727 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_long_pool_set()
2730 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
2751 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, in mvpp2_bm_pool_put() argument
2755 if (port->priv->hw_version == MVPP22) { in mvpp2_bm_pool_put()
2767 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val); in mvpp2_bm_pool_put()
2775 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); in mvpp2_bm_pool_put()
2776 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); in mvpp2_bm_pool_put()
2780 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm, in mvpp2_pool_refill() argument
2786 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); in mvpp2_pool_refill()
2790 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, in mvpp2_bm_bufs_add() argument
2796 (buf_num + bm_pool->buf_num > bm_pool->size)) { in mvpp2_bm_bufs_add()
2797 netdev_err(port->dev, in mvpp2_bm_bufs_add()
2799 buf_num, bm_pool->id); in mvpp2_bm_bufs_add()
2804 mvpp2_bm_pool_put(port, bm_pool->id, in mvpp2_bm_bufs_add()
2811 bm_pool->buf_num += i; in mvpp2_bm_bufs_add()
2820 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, in mvpp2_bm_pool_use() argument
2823 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; in mvpp2_bm_pool_use()
2826 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) { in mvpp2_bm_pool_use()
2827 netdev_err(port->dev, "mixing pool types is forbidden\n"); in mvpp2_bm_pool_use()
2831 if (new_pool->type == MVPP2_BM_FREE) in mvpp2_bm_pool_use()
2832 new_pool->type = type; in mvpp2_bm_pool_use()
2837 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) || in mvpp2_bm_pool_use()
2838 (new_pool->pkt_size == 0)) { in mvpp2_bm_pool_use()
2844 pkts_num = new_pool->buf_num; in mvpp2_bm_pool_use()
2851 port->priv, new_pool); in mvpp2_bm_pool_use()
2853 new_pool->pkt_size = pkt_size; in mvpp2_bm_pool_use()
2856 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); in mvpp2_bm_pool_use()
2859 new_pool->id, num, pkts_num); in mvpp2_bm_pool_use()
2868 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) in mvpp2_swf_bm_pool_init() argument
2872 if (!port->pool_long) { in mvpp2_swf_bm_pool_init()
2873 port->pool_long = in mvpp2_swf_bm_pool_init()
2874 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id), in mvpp2_swf_bm_pool_init()
2876 port->pkt_size); in mvpp2_swf_bm_pool_init()
2877 if (!port->pool_long) in mvpp2_swf_bm_pool_init()
2878 return -ENOMEM; in mvpp2_swf_bm_pool_init()
2880 port->pool_long->port_map |= (1 << port->id); in mvpp2_swf_bm_pool_init()
2883 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); in mvpp2_swf_bm_pool_init()
2889 /* Port configuration routines */
2891 static void mvpp2_port_mii_set(struct mvpp2_port *port) in mvpp2_port_mii_set() argument
2895 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_mii_set()
2897 switch (port->phy_interface) { in mvpp2_port_mii_set()
2908 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_mii_set()
2911 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port) in mvpp2_port_fc_adv_enable() argument
2915 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_fc_adv_enable()
2917 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_fc_adv_enable()
2920 static void mvpp2_port_enable(struct mvpp2_port *port) in mvpp2_port_enable() argument
2924 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
2927 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
2930 static void mvpp2_port_disable(struct mvpp2_port *port) in mvpp2_port_disable() argument
2934 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
2936 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
2940 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) in mvpp2_port_periodic_xon_disable() argument
2944 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & in mvpp2_port_periodic_xon_disable()
2946 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_periodic_xon_disable()
2949 /* Configure loopback port */
2950 static void mvpp2_port_loopback_set(struct mvpp2_port *port) in mvpp2_port_loopback_set() argument
2954 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
2956 if (port->speed == 1000) in mvpp2_port_loopback_set()
2961 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) in mvpp2_port_loopback_set()
2966 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
2969 static void mvpp2_port_reset(struct mvpp2_port *port) in mvpp2_port_reset() argument
2973 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_port_reset()
2975 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_port_reset()
2977 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_port_reset()
2982 /* Change maximum receive size of the port */
2983 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) in mvpp2_gmac_max_rx_size_set() argument
2987 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2989 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << in mvpp2_gmac_max_rx_size_set()
2991 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2997 static int gop_gmac_reset(struct mvpp2_port *port, int reset) in gop_gmac_reset() argument
3001 /* read - modify - write */ in gop_gmac_reset()
3002 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gmac_reset()
3007 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gmac_reset()
3015 * Configure port to working with Gig PCS or don't.
3017 static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en) in gop_gpcs_mode_cfg() argument
3021 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_mode_cfg()
3026 /* enable / disable PCS on this port */ in gop_gpcs_mode_cfg()
3027 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_mode_cfg()
3032 static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en) in gop_bypass_clk_cfg() argument
3036 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_bypass_clk_cfg()
3041 /* enable / disable PCS on this port */ in gop_bypass_clk_cfg()
3042 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_bypass_clk_cfg()
3047 static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port) in gop_gmac_sgmii2_5_cfg() argument
3056 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii2_5_cfg()
3059 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii2_5_cfg()
3062 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii2_5_cfg()
3068 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii2_5_cfg()
3070 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii2_5_cfg()
3072 * Configure GIG MAC to 1000Base-X mode connected to a fiber in gop_gmac_sgmii2_5_cfg()
3076 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii2_5_cfg()
3086 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in gop_gmac_sgmii2_5_cfg()
3089 static void gop_gmac_sgmii_cfg(struct mvpp2_port *port) in gop_gmac_sgmii_cfg() argument
3098 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii_cfg()
3101 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_sgmii_cfg()
3104 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii_cfg()
3110 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_sgmii_cfg()
3112 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii_cfg()
3115 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_sgmii_cfg()
3124 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in gop_gmac_sgmii_cfg()
3127 static void gop_gmac_rgmii_cfg(struct mvpp2_port *port) in gop_gmac_rgmii_cfg() argument
3136 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_rgmii_cfg()
3139 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in gop_gmac_rgmii_cfg()
3142 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_rgmii_cfg()
3148 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); in gop_gmac_rgmii_cfg()
3150 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_rgmii_cfg()
3153 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_rgmii_cfg()
3161 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in gop_gmac_rgmii_cfg()
3165 static int gop_gmac_mode_cfg(struct mvpp2_port *port) in gop_gmac_mode_cfg() argument
3170 switch (port->phy_interface) { in gop_gmac_mode_cfg()
3172 if (port->phy_speed == 2500) in gop_gmac_mode_cfg()
3173 gop_gmac_sgmii2_5_cfg(port); in gop_gmac_mode_cfg()
3175 gop_gmac_sgmii_cfg(port); in gop_gmac_mode_cfg()
3180 gop_gmac_rgmii_cfg(port); in gop_gmac_mode_cfg()
3184 return -1; in gop_gmac_mode_cfg()
3187 /* Jumbo frame support - 0x1400*2= 0x2800 bytes */ in gop_gmac_mode_cfg()
3188 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_mode_cfg()
3191 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in gop_gmac_mode_cfg()
3194 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in gop_gmac_mode_cfg()
3196 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in gop_gmac_mode_cfg()
3201 static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port) in gop_xlg_2_gig_mac_cfg() argument
3206 if (port->gop_id > 0) in gop_xlg_2_gig_mac_cfg()
3210 val = readl(port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_2_gig_mac_cfg()
3213 writel(val, port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_2_gig_mac_cfg()
3216 static int gop_gpcs_reset(struct mvpp2_port *port, int reset) in gop_gpcs_reset() argument
3220 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_reset()
3225 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in gop_gpcs_reset()
3231 static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes) in gop_xpcs_mode() argument
3247 return -1; in gop_xpcs_mode()
3251 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_mode()
3255 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_mode()
3260 static int gop_mpcs_mode(struct mvpp2_port *port) in gop_mpcs_mode() argument
3265 val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL); in gop_mpcs_mode()
3267 writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL); in gop_mpcs_mode()
3270 val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET); in gop_mpcs_mode()
3273 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET); in gop_mpcs_mode()
3279 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET); in gop_mpcs_mode()
3285 static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes) in gop_xlg_mac_mode_cfg() argument
3290 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_mode_cfg()
3292 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_mode_cfg()
3294 val = readl(port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_mac_mode_cfg()
3297 writel(val, port->base + MVPP22_XLG_CTRL3_REG); in gop_xlg_mac_mode_cfg()
3299 /* read - modify - write */ in gop_xlg_mac_mode_cfg()
3300 val = readl(port->base + MVPP22_XLG_CTRL4_REG); in gop_xlg_mac_mode_cfg()
3305 writel(val, port->base + MVPP22_XLG_CTRL4_REG); in gop_xlg_mac_mode_cfg()
3308 val = readl(port->base + MVPP22_XLG_CTRL1_REG); in gop_xlg_mac_mode_cfg()
3311 writel(val, port->base + MVPP22_XLG_CTRL1_REG); in gop_xlg_mac_mode_cfg()
3314 val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG); in gop_xlg_mac_mode_cfg()
3317 writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG); in gop_xlg_mac_mode_cfg()
3323 static int gop_xpcs_reset(struct mvpp2_port *port, int reset) in gop_xpcs_reset() argument
3327 /* read - modify - write */ in gop_xpcs_reset()
3328 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_reset()
3333 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); in gop_xpcs_reset()
3339 static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset) in gop_xlg_mac_reset() argument
3343 /* read - modify - write */ in gop_xlg_mac_reset()
3344 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_reset()
3349 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_reset()
3357 * Init physical port. Configures the port mode and all it's elements
3359 * Does not verify that the selected mode/port number is valid at the
3362 static int gop_port_init(struct mvpp2_port *port) in gop_port_init() argument
3364 int mac_num = port->gop_id; in gop_port_init()
3368 netdev_err(NULL, "%s: illegal port number %d", __func__, in gop_port_init()
3370 return -1; in gop_port_init()
3373 switch (port->phy_interface) { in gop_port_init()
3376 gop_gmac_reset(port, 1); in gop_port_init()
3379 gop_gpcs_mode_cfg(port, 0); in gop_port_init()
3380 gop_bypass_clk_cfg(port, 1); in gop_port_init()
3383 gop_gmac_mode_cfg(port); in gop_port_init()
3385 gop_gpcs_reset(port, 0); in gop_port_init()
3388 gop_gmac_reset(port, 0); in gop_port_init()
3393 gop_gpcs_mode_cfg(port, 1); in gop_port_init()
3396 gop_gmac_mode_cfg(port); in gop_port_init()
3398 gop_xlg_2_gig_mac_cfg(port); in gop_port_init()
3401 gop_gpcs_reset(port, 0); in gop_port_init()
3403 gop_gmac_reset(port, 0); in gop_port_init()
3410 gop_xpcs_mode(port, num_of_act_lanes); in gop_port_init()
3411 gop_mpcs_mode(port); in gop_port_init()
3413 gop_xlg_mac_mode_cfg(port, num_of_act_lanes); in gop_port_init()
3416 gop_xpcs_reset(port, 0); in gop_port_init()
3419 gop_xlg_mac_reset(port, 0); in gop_port_init()
3423 netdev_err(NULL, "%s: Requested port mode (%d) not supported\n", in gop_port_init()
3424 __func__, port->phy_interface); in gop_port_init()
3425 return -1; in gop_port_init()
3431 static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable) in gop_xlg_mac_port_enable() argument
3435 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_port_enable()
3437 /* Enable port and MIB counters update */ in gop_xlg_mac_port_enable()
3441 /* Disable port */ in gop_xlg_mac_port_enable()
3444 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in gop_xlg_mac_port_enable()
3447 static void gop_port_enable(struct mvpp2_port *port, int enable) in gop_port_enable() argument
3449 switch (port->phy_interface) { in gop_port_enable()
3454 mvpp2_port_enable(port); in gop_port_enable()
3456 mvpp2_port_disable(port); in gop_port_enable()
3460 gop_xlg_mac_port_enable(port, enable); in gop_port_enable()
3464 netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__, in gop_port_enable()
3465 port->phy_interface); in gop_port_enable()
3473 return readl(priv->rfu1_base + offset); in gop_rfu1_read()
3478 writel(data, priv->rfu1_base + offset); in gop_rfu1_write()
3641 /* De-assert the relevant port HB reset */ in gop_netc_mac_to_xgmii()
3667 /* De-assert the relevant port HB reset */ in gop_netc_mac_to_sgmii()
3675 u32 c = priv->netc_config; in gop_netc_init()
3700 /* De-assert GOP unit reset */ in gop_netc_init()
3707 /* Set defaults to the MVPP2 port */
3708 static void mvpp2_defaults_set(struct mvpp2_port *port) in mvpp2_defaults_set() argument
3712 if (port->priv->hw_version == MVPP21) { in mvpp2_defaults_set()
3713 /* Configure port to loopback if needed */ in mvpp2_defaults_set()
3714 if (port->flags & MVPP2_F_LOOPBACK) in mvpp2_defaults_set()
3715 mvpp2_port_loopback_set(port); in mvpp2_defaults_set()
3718 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
3721 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); in mvpp2_defaults_set()
3722 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
3726 tx_port_num = mvpp2_egress_port(port); in mvpp2_defaults_set()
3727 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set()
3729 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); in mvpp2_defaults_set()
3733 ptxq = mvpp2_txq_phys(port->id, queue); in mvpp2_defaults_set()
3734 mvpp2_write(port->priv, in mvpp2_defaults_set()
3741 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8); in mvpp2_defaults_set()
3742 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); in mvpp2_defaults_set()
3746 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); in mvpp2_defaults_set()
3748 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_defaults_set()
3751 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), in mvpp2_defaults_set()
3757 queue = port->rxqs[lrxq]->id; in mvpp2_defaults_set()
3758 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_defaults_set()
3761 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
3766 static void mvpp2_ingress_enable(struct mvpp2_port *port) in mvpp2_ingress_enable() argument
3772 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_enable()
3773 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_enable()
3775 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
3779 static void mvpp2_ingress_disable(struct mvpp2_port *port) in mvpp2_ingress_disable() argument
3785 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_disable()
3786 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_disable()
3788 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
3793 * - HW starts take descriptors from DRAM
3795 static void mvpp2_egress_enable(struct mvpp2_port *port) in mvpp2_egress_enable() argument
3799 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_enable()
3804 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_egress_enable()
3806 if (txq->descs != NULL) in mvpp2_egress_enable()
3810 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable()
3811 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); in mvpp2_egress_enable()
3815 * - HW doesn't take descriptors from DRAM
3817 static void mvpp2_egress_disable(struct mvpp2_port *port) in mvpp2_egress_disable() argument
3821 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_disable()
3824 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable()
3825 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & in mvpp2_egress_disable()
3828 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, in mvpp2_egress_disable()
3835 netdev_warn(port->dev, in mvpp2_egress_disable()
3843 /* Check port TX Command register that all in mvpp2_egress_disable()
3846 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); in mvpp2_egress_disable()
3854 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) in mvpp2_rxq_received() argument
3856 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); in mvpp2_rxq_received()
3865 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, in mvpp2_rxq_status_update() argument
3873 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); in mvpp2_rxq_status_update()
3880 int rx_desc = rxq->next_desc_to_proc; in mvpp2_rxq_next_desc_get()
3882 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); in mvpp2_rxq_next_desc_get()
3883 prefetch(rxq->descs + rxq->next_desc_to_proc); in mvpp2_rxq_next_desc_get()
3884 return rxq->descs + rx_desc; in mvpp2_rxq_next_desc_get()
3888 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, in mvpp2_rxq_offset_set() argument
3896 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_offset_set()
3903 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()
3907 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port, in mvpp2_bm_cookie_build() argument
3913 pool = (mvpp2_rxdesc_status_get(port, rx_desc) & in mvpp2_bm_cookie_build()
3924 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port, in mvpp2_txq_pend_desc_num_get() argument
3929 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_pend_desc_num_get()
3930 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_pend_desc_num_get()
3939 int tx_desc = txq->next_desc_to_proc; in mvpp2_txq_next_desc_get()
3941 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); in mvpp2_txq_next_desc_get()
3942 return txq->descs + tx_desc; in mvpp2_txq_next_desc_get()
3946 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) in mvpp2_aggr_txq_pend_desc_add() argument
3948 /* aggregated access - relevant TXQ number is written in TX desc */ in mvpp2_aggr_txq_pend_desc_add()
3949 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending); in mvpp2_aggr_txq_pend_desc_add()
3954 * Per-CPU access
3956 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, in mvpp2_txq_sent_desc_proc() argument
3962 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id)); in mvpp2_txq_sent_desc_proc()
3970 struct mvpp2_port *port = arg; in mvpp2_txq_sent_counter_clear() local
3974 int id = port->txqs[queue]->id; in mvpp2_txq_sent_counter_clear()
3976 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id)); in mvpp2_txq_sent_counter_clear()
3981 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) in mvpp2_txp_max_tx_size_set() argument
3986 mtu = port->pkt_size * 8; in mvpp2_txp_max_tx_size_set()
3994 tx_port_num = mvpp2_egress_port(port); in mvpp2_txp_max_tx_size_set()
3995 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set()
3998 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); in mvpp2_txp_max_tx_size_set()
4001 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); in mvpp2_txp_max_tx_size_set()
4004 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); in mvpp2_txp_max_tx_size_set()
4010 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_txp_max_tx_size_set()
4014 val = mvpp2_read(port->priv, in mvpp2_txp_max_tx_size_set()
4022 mvpp2_write(port->priv, in mvpp2_txp_max_tx_size_set()
4030 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, in mvpp2_txq_bufs_free() argument
4040 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, in mvpp2_get_rx_queue() argument
4043 int queue = fls(cause) - 1; in mvpp2_get_rx_queue()
4045 return port->rxqs[queue]; in mvpp2_get_rx_queue()
4048 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, in mvpp2_get_tx_queue() argument
4051 int queue = fls(cause) - 1; in mvpp2_get_tx_queue()
4053 return port->txqs[queue]; in mvpp2_get_tx_queue()
4067 aggr_txq->descs = buffer_loc.aggr_tx_descs; in mvpp2_aggr_txq_init()
4068 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs; in mvpp2_aggr_txq_init()
4069 if (!aggr_txq->descs) in mvpp2_aggr_txq_init()
4070 return -ENOMEM; in mvpp2_aggr_txq_init()
4073 BUG_ON(aggr_txq->descs != in mvpp2_aggr_txq_init()
4074 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE)); in mvpp2_aggr_txq_init()
4076 aggr_txq->last_desc = aggr_txq->size - 1; in mvpp2_aggr_txq_init()
4079 aggr_txq->next_desc_to_proc = mvpp2_read(priv, in mvpp2_aggr_txq_init()
4085 if (priv->hw_version == MVPP21) in mvpp2_aggr_txq_init()
4086 txq_dma = aggr_txq->descs_dma; in mvpp2_aggr_txq_init()
4088 txq_dma = aggr_txq->descs_dma >> in mvpp2_aggr_txq_init()
4098 static int mvpp2_rxq_init(struct mvpp2_port *port, in mvpp2_rxq_init() argument
4104 rxq->size = port->rx_ring_size; in mvpp2_rxq_init()
4107 rxq->descs = buffer_loc.rx_descs; in mvpp2_rxq_init()
4108 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs; in mvpp2_rxq_init()
4109 if (!rxq->descs) in mvpp2_rxq_init()
4110 return -ENOMEM; in mvpp2_rxq_init()
4112 BUG_ON(rxq->descs != in mvpp2_rxq_init()
4113 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE)); in mvpp2_rxq_init()
4115 rxq->last_desc = rxq->size - 1; in mvpp2_rxq_init()
4117 /* Zero occupied and non-occupied counters - direct access */ in mvpp2_rxq_init()
4118 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_init()
4120 /* Set Rx descriptors queue starting address - indirect access */ in mvpp2_rxq_init()
4121 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_init()
4122 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_init()
4123 rxq_dma = rxq->descs_dma; in mvpp2_rxq_init()
4125 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; in mvpp2_rxq_init()
4126 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); in mvpp2_rxq_init()
4127 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); in mvpp2_rxq_init()
4128 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0); in mvpp2_rxq_init()
4131 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); in mvpp2_rxq_init()
4134 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); in mvpp2_rxq_init()
4140 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, in mvpp2_rxq_drop_pkts() argument
4145 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rxq_drop_pkts()
4151 u32 bm = mvpp2_bm_cookie_build(port, rx_desc); in mvpp2_rxq_drop_pkts()
4153 mvpp2_pool_refill(port, bm, in mvpp2_rxq_drop_pkts()
4154 mvpp2_rxdesc_dma_addr_get(port, rx_desc), in mvpp2_rxq_drop_pkts()
4155 mvpp2_rxdesc_cookie_get(port, rx_desc)); in mvpp2_rxq_drop_pkts()
4157 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); in mvpp2_rxq_drop_pkts()
4161 static void mvpp2_rxq_deinit(struct mvpp2_port *port, in mvpp2_rxq_deinit() argument
4164 mvpp2_rxq_drop_pkts(port, rxq); in mvpp2_rxq_deinit()
4166 rxq->descs = NULL; in mvpp2_rxq_deinit()
4167 rxq->last_desc = 0; in mvpp2_rxq_deinit()
4168 rxq->next_desc_to_proc = 0; in mvpp2_rxq_deinit()
4169 rxq->descs_dma = 0; in mvpp2_rxq_deinit()
4174 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_deinit()
4175 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_deinit()
4176 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0); in mvpp2_rxq_deinit()
4177 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0); in mvpp2_rxq_deinit()
4181 static int mvpp2_txq_init(struct mvpp2_port *port, in mvpp2_txq_init() argument
4188 txq->size = port->tx_ring_size; in mvpp2_txq_init()
4191 txq->descs = buffer_loc.tx_descs; in mvpp2_txq_init()
4192 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs; in mvpp2_txq_init()
4193 if (!txq->descs) in mvpp2_txq_init()
4194 return -ENOMEM; in mvpp2_txq_init()
4197 BUG_ON(txq->descs != in mvpp2_txq_init()
4198 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE)); in mvpp2_txq_init()
4200 txq->last_desc = txq->size - 1; in mvpp2_txq_init()
4202 /* Set Tx descriptors queue starting address - indirect access */ in mvpp2_txq_init()
4203 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_init()
4204 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma); in mvpp2_txq_init()
4205 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size & in mvpp2_txq_init()
4207 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0); in mvpp2_txq_init()
4208 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG, in mvpp2_txq_init()
4209 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); in mvpp2_txq_init()
4210 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_init()
4212 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val); in mvpp2_txq_init()
4216 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT in mvpp2_txq_init()
4220 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + in mvpp2_txq_init()
4221 (txq->log_id * desc_per_txq); in mvpp2_txq_init()
4223 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, in mvpp2_txq_init()
4227 /* WRR / EJP configuration - indirect access */ in mvpp2_txq_init()
4228 tx_port_num = mvpp2_egress_port(port); in mvpp2_txq_init()
4229 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
4231 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); in mvpp2_txq_init()
4235 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); in mvpp2_txq_init()
4238 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), in mvpp2_txq_init()
4242 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); in mvpp2_txq_init()
4243 txq_pcpu->size = txq->size; in mvpp2_txq_init()
4250 static void mvpp2_txq_deinit(struct mvpp2_port *port, in mvpp2_txq_deinit() argument
4253 txq->descs = NULL; in mvpp2_txq_deinit()
4254 txq->last_desc = 0; in mvpp2_txq_deinit()
4255 txq->next_desc_to_proc = 0; in mvpp2_txq_deinit()
4256 txq->descs_dma = 0; in mvpp2_txq_deinit()
4259 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); in mvpp2_txq_deinit()
4262 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_deinit()
4263 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0); in mvpp2_txq_deinit()
4264 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0); in mvpp2_txq_deinit()
4268 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) in mvpp2_txq_clean() argument
4274 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_clean()
4275 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG); in mvpp2_txq_clean()
4277 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4285 netdev_warn(port->dev, in mvpp2_txq_clean()
4286 "port %d: cleaning queue %d timed out\n", in mvpp2_txq_clean()
4287 port->id, txq->log_id); in mvpp2_txq_clean()
4293 pending = mvpp2_txq_pend_desc_num_get(port, txq); in mvpp2_txq_clean()
4297 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4300 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); in mvpp2_txq_clean()
4303 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); in mvpp2_txq_clean()
4306 txq_pcpu->count = 0; in mvpp2_txq_clean()
4307 txq_pcpu->txq_put_index = 0; in mvpp2_txq_clean()
4308 txq_pcpu->txq_get_index = 0; in mvpp2_txq_clean()
4313 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) in mvpp2_cleanup_txqs() argument
4319 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); in mvpp2_cleanup_txqs()
4322 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
4323 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4326 txq = port->txqs[queue]; in mvpp2_cleanup_txqs()
4327 mvpp2_txq_clean(port, txq); in mvpp2_cleanup_txqs()
4328 mvpp2_txq_deinit(port, txq); in mvpp2_cleanup_txqs()
4331 mvpp2_txq_sent_counter_clear(port); in mvpp2_cleanup_txqs()
4333 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
4334 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4338 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) in mvpp2_cleanup_rxqs() argument
4343 mvpp2_rxq_deinit(port, port->rxqs[queue]); in mvpp2_cleanup_rxqs()
4346 /* Init all Rx queues for port */
4347 static int mvpp2_setup_rxqs(struct mvpp2_port *port) in mvpp2_setup_rxqs() argument
4352 err = mvpp2_rxq_init(port, port->rxqs[queue]); in mvpp2_setup_rxqs()
4359 mvpp2_cleanup_rxqs(port); in mvpp2_setup_rxqs()
4363 /* Init all tx queues for port */
4364 static int mvpp2_setup_txqs(struct mvpp2_port *port) in mvpp2_setup_txqs() argument
4370 txq = port->txqs[queue]; in mvpp2_setup_txqs()
4371 err = mvpp2_txq_init(port, txq); in mvpp2_setup_txqs()
4376 mvpp2_txq_sent_counter_clear(port); in mvpp2_setup_txqs()
4380 mvpp2_cleanup_txqs(port); in mvpp2_setup_txqs()
4385 static void mvpp2_link_event(struct mvpp2_port *port) in mvpp2_link_event() argument
4387 struct phy_device *phydev = port->phy_dev; in mvpp2_link_event()
4391 if (phydev->link) { in mvpp2_link_event()
4392 if ((port->speed != phydev->speed) || in mvpp2_link_event()
4393 (port->duplex != phydev->duplex)) { in mvpp2_link_event()
4396 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4403 if (phydev->duplex) in mvpp2_link_event()
4406 if (phydev->speed == SPEED_1000) in mvpp2_link_event()
4408 else if (phydev->speed == SPEED_100) in mvpp2_link_event()
4411 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4413 port->duplex = phydev->duplex; in mvpp2_link_event()
4414 port->speed = phydev->speed; in mvpp2_link_event()
4418 if (phydev->link != port->link) { in mvpp2_link_event()
4419 if (!phydev->link) { in mvpp2_link_event()
4420 port->duplex = -1; in mvpp2_link_event()
4421 port->speed = 0; in mvpp2_link_event()
4424 port->link = phydev->link; in mvpp2_link_event()
4429 if (phydev->link) { in mvpp2_link_event()
4430 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4433 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_link_event()
4434 mvpp2_egress_enable(port); in mvpp2_link_event()
4435 mvpp2_ingress_enable(port); in mvpp2_link_event()
4437 mvpp2_ingress_disable(port); in mvpp2_link_event()
4438 mvpp2_egress_disable(port); in mvpp2_link_event()
4446 static void mvpp2_rx_error(struct mvpp2_port *port, in mvpp2_rx_error() argument
4449 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_rx_error()
4450 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); in mvpp2_rx_error()
4454 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n", in mvpp2_rx_error()
4458 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n", in mvpp2_rx_error()
4462 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n", in mvpp2_rx_error()
4469 static int mvpp2_rx_refill(struct mvpp2_port *port, in mvpp2_rx_refill() argument
4473 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr); in mvpp2_rx_refill()
4477 /* Set hw internals when starting port */
4478 static void mvpp2_start_dev(struct mvpp2_port *port) in mvpp2_start_dev() argument
4480 switch (port->phy_interface) { in mvpp2_start_dev()
4484 mvpp2_gmac_max_rx_size_set(port); in mvpp2_start_dev()
4489 mvpp2_txp_max_tx_size_set(port); in mvpp2_start_dev()
4491 if (port->priv->hw_version == MVPP21) in mvpp2_start_dev()
4492 mvpp2_port_enable(port); in mvpp2_start_dev()
4494 gop_port_enable(port, 1); in mvpp2_start_dev()
4497 /* Set hw internals when stopping port */
4498 static void mvpp2_stop_dev(struct mvpp2_port *port) in mvpp2_stop_dev() argument
4501 mvpp2_ingress_disable(port); in mvpp2_stop_dev()
4503 mvpp2_egress_disable(port); in mvpp2_stop_dev()
4505 if (port->priv->hw_version == MVPP21) in mvpp2_stop_dev()
4506 mvpp2_port_disable(port); in mvpp2_stop_dev()
4508 gop_port_enable(port, 0); in mvpp2_stop_dev()
4511 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port) in mvpp2_phy_connect() argument
4515 if (!port->init || port->link == 0) { in mvpp2_phy_connect()
4516 phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev, in mvpp2_phy_connect()
4517 port->phy_interface); in mvpp2_phy_connect()
4518 port->phy_dev = phy_dev; in mvpp2_phy_connect()
4520 netdev_err(port->dev, "cannot connect to phy\n"); in mvpp2_phy_connect()
4521 return -ENODEV; in mvpp2_phy_connect()
4523 phy_dev->supported &= PHY_GBIT_FEATURES; in mvpp2_phy_connect()
4524 phy_dev->advertising = phy_dev->supported; in mvpp2_phy_connect()
4526 port->phy_dev = phy_dev; in mvpp2_phy_connect()
4527 port->link = 0; in mvpp2_phy_connect()
4528 port->duplex = 0; in mvpp2_phy_connect()
4529 port->speed = 0; in mvpp2_phy_connect()
4533 if (!phy_dev->link) { in mvpp2_phy_connect()
4534 printf("%s: No link\n", phy_dev->dev->name); in mvpp2_phy_connect()
4535 return -1; in mvpp2_phy_connect()
4538 port->init = 1; in mvpp2_phy_connect()
4540 mvpp2_egress_enable(port); in mvpp2_phy_connect()
4541 mvpp2_ingress_enable(port); in mvpp2_phy_connect()
4547 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port) in mvpp2_open() argument
4553 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true); in mvpp2_open()
4558 err = mvpp2_prs_mac_da_accept(port->priv, port->id, in mvpp2_open()
4559 port->dev_addr, true); in mvpp2_open()
4564 err = mvpp2_prs_def_flow(port); in mvpp2_open()
4571 err = mvpp2_setup_rxqs(port); in mvpp2_open()
4573 netdev_err(port->dev, "cannot allocate Rx queues\n"); in mvpp2_open()
4577 err = mvpp2_setup_txqs(port); in mvpp2_open()
4579 netdev_err(port->dev, "cannot allocate Tx queues\n"); in mvpp2_open()
4583 if (port->phy_node) { in mvpp2_open()
4584 err = mvpp2_phy_connect(dev, port); in mvpp2_open()
4588 mvpp2_link_event(port); in mvpp2_open()
4590 mvpp2_egress_enable(port); in mvpp2_open()
4591 mvpp2_ingress_enable(port); in mvpp2_open()
4594 mvpp2_start_dev(port); in mvpp2_open()
4599 /* No Device ops here in U-Boot */
4603 static void mvpp2_port_power_up(struct mvpp2_port *port) in mvpp2_port_power_up() argument
4605 struct mvpp2 *priv = port->priv; in mvpp2_port_power_up()
4608 if (priv->hw_version == MVPP21) in mvpp2_port_power_up()
4609 mvpp2_port_mii_set(port); in mvpp2_port_power_up()
4610 mvpp2_port_periodic_xon_disable(port); in mvpp2_port_power_up()
4611 if (priv->hw_version == MVPP21) in mvpp2_port_power_up()
4612 mvpp2_port_fc_adv_enable(port); in mvpp2_port_power_up()
4613 mvpp2_port_reset(port); in mvpp2_port_power_up()
4616 /* Initialize port HW */
4617 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) in mvpp2_port_init() argument
4619 struct mvpp2 *priv = port->priv; in mvpp2_port_init()
4623 if (port->first_rxq + rxq_number > in mvpp2_port_init()
4624 MVPP2_MAX_PORTS * priv->max_port_rxqs) in mvpp2_port_init()
4625 return -EINVAL; in mvpp2_port_init()
4627 /* Disable port */ in mvpp2_port_init()
4628 mvpp2_egress_disable(port); in mvpp2_port_init()
4629 if (priv->hw_version == MVPP21) in mvpp2_port_init()
4630 mvpp2_port_disable(port); in mvpp2_port_init()
4632 gop_port_enable(port, 0); in mvpp2_port_init()
4634 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs), in mvpp2_port_init()
4636 if (!port->txqs) in mvpp2_port_init()
4637 return -ENOMEM; in mvpp2_port_init()
4639 /* Associate physical Tx queues to this port and initialize. in mvpp2_port_init()
4643 int queue_phy_id = mvpp2_txq_phys(port->id, queue); in mvpp2_port_init()
4648 return -ENOMEM; in mvpp2_port_init()
4650 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu), in mvpp2_port_init()
4652 if (!txq->pcpu) in mvpp2_port_init()
4653 return -ENOMEM; in mvpp2_port_init()
4655 txq->id = queue_phy_id; in mvpp2_port_init()
4656 txq->log_id = queue; in mvpp2_port_init()
4657 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; in mvpp2_port_init()
4659 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); in mvpp2_port_init()
4660 txq_pcpu->cpu = cpu; in mvpp2_port_init()
4663 port->txqs[queue] = txq; in mvpp2_port_init()
4666 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs), in mvpp2_port_init()
4668 if (!port->rxqs) in mvpp2_port_init()
4669 return -ENOMEM; in mvpp2_port_init()
4671 /* Allocate and initialize Rx queue for this port */ in mvpp2_port_init()
4675 /* Map physical Rx queue to port's logical Rx queue */ in mvpp2_port_init()
4678 return -ENOMEM; in mvpp2_port_init()
4680 rxq->id = port->first_rxq + queue; in mvpp2_port_init()
4681 rxq->port = port->id; in mvpp2_port_init()
4682 rxq->logic_rxq = queue; in mvpp2_port_init()
4684 port->rxqs[queue] = rxq; in mvpp2_port_init()
4690 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_port_init()
4692 rxq->size = port->rx_ring_size; in mvpp2_port_init()
4693 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; in mvpp2_port_init()
4694 rxq->time_coal = MVPP2_RX_COAL_USEC; in mvpp2_port_init()
4697 mvpp2_ingress_disable(port); in mvpp2_port_init()
4699 /* Port default configuration */ in mvpp2_port_init()
4700 mvpp2_defaults_set(port); in mvpp2_port_init()
4702 /* Port's classifier configuration */ in mvpp2_port_init()
4703 mvpp2_cls_oversize_rxq_set(port); in mvpp2_port_init()
4704 mvpp2_cls_port_config(port); in mvpp2_port_init()
4707 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN); in mvpp2_port_init()
4710 err = mvpp2_swf_bm_pool_init(port); in mvpp2_port_init()
4717 static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) in phy_info_parse() argument
4724 int phy_mode = -1; in phy_info_parse()
4727 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy"); in phy_info_parse()
4730 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0); in phy_info_parse()
4732 dev_err(&pdev->dev, "could not find phy address\n"); in phy_info_parse()
4733 return -1; in phy_info_parse()
4735 mdio_off = fdt_parent_offset(gd->fdt_blob, phy_node); in phy_info_parse()
4737 /* TODO: This WA for mdio issue. U-boot 2017 don't have in phy_info_parse()
4744 mdio_addr = fdtdec_get_uint(gd->fdt_blob, in phy_info_parse()
4747 cp_node = fdt_parent_offset(gd->fdt_blob, mdio_off); in phy_info_parse()
4748 mdio_addr |= fdt_get_base_address((void *)gd->fdt_blob, in phy_info_parse()
4751 port->priv->mdio_base = (void *)mdio_addr; in phy_info_parse()
4753 if (port->priv->mdio_base < 0) { in phy_info_parse()
4754 dev_err(&pdev->dev, "could not find mdio base address\n"); in phy_info_parse()
4755 return -1; in phy_info_parse()
4761 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL); in phy_info_parse()
4764 if (phy_mode == -1) { in phy_info_parse()
4765 dev_err(&pdev->dev, "incorrect phy mode\n"); in phy_info_parse()
4766 return -EINVAL; in phy_info_parse()
4769 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1); in phy_info_parse()
4770 if (id == -1) { in phy_info_parse()
4771 dev_err(&pdev->dev, "missing port-id value\n"); in phy_info_parse()
4772 return -EINVAL; in phy_info_parse()
4776 gpio_request_by_name(dev, "phy-reset-gpios", 0, in phy_info_parse()
4777 &port->phy_reset_gpio, GPIOD_IS_OUT); in phy_info_parse()
4778 gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0, in phy_info_parse()
4779 &port->phy_tx_disable_gpio, GPIOD_IS_OUT); in phy_info_parse()
4784 * Not sure if this DT property "phy-speed" will get accepted, so in phy_info_parse()
4787 /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */ in phy_info_parse()
4788 port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node, in phy_info_parse()
4789 "phy-speed", 1000); in phy_info_parse()
4791 port->id = id; in phy_info_parse()
4792 if (port->priv->hw_version == MVPP21) in phy_info_parse()
4793 port->first_rxq = port->id * rxq_number; in phy_info_parse()
4795 port->first_rxq = port->id * port->priv->max_port_rxqs; in phy_info_parse()
4796 port->phy_node = phy_node; in phy_info_parse()
4797 port->phy_interface = phy_mode; in phy_info_parse()
4798 port->phyaddr = phyaddr; in phy_info_parse()
4804 /* Port GPIO initialization */
4805 static void mvpp2_gpio_init(struct mvpp2_port *port) in mvpp2_gpio_init() argument
4807 if (dm_gpio_is_valid(&port->phy_reset_gpio)) { in mvpp2_gpio_init()
4808 dm_gpio_set_value(&port->phy_reset_gpio, 0); in mvpp2_gpio_init()
4810 dm_gpio_set_value(&port->phy_reset_gpio, 1); in mvpp2_gpio_init()
4813 if (dm_gpio_is_valid(&port->phy_tx_disable_gpio)) in mvpp2_gpio_init()
4814 dm_gpio_set_value(&port->phy_tx_disable_gpio, 0); in mvpp2_gpio_init()
4820 struct mvpp2_port *port, in mvpp2_port_probe() argument
4826 port->tx_ring_size = MVPP2_MAX_TXD; in mvpp2_port_probe()
4827 port->rx_ring_size = MVPP2_MAX_RXD; in mvpp2_port_probe()
4829 err = mvpp2_port_init(dev, port); in mvpp2_port_probe()
4831 dev_err(&pdev->dev, "failed to init port %d\n", port->id); in mvpp2_port_probe()
4834 mvpp2_port_power_up(port); in mvpp2_port_probe()
4837 mvpp2_gpio_init(port); in mvpp2_port_probe()
4840 priv->port_list[port->id] = port; in mvpp2_port_probe()
4841 priv->num_ports++; in mvpp2_port_probe()
4862 for (i = 0; i < dram->num_cs; i++) { in mvpp2_conf_mbus_windows()
4863 const struct mbus_dram_window *cs = dram->cs + i; in mvpp2_conf_mbus_windows()
4866 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | in mvpp2_conf_mbus_windows()
4867 dram->mbus_dram_target_id); in mvpp2_conf_mbus_windows()
4870 (cs->size - 1) & 0xffff0000); in mvpp2_conf_mbus_windows()
4881 int port; in mvpp2_rx_fifo_init() local
4883 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_rx_fifo_init()
4884 if (priv->hw_version == MVPP22) { in mvpp2_rx_fifo_init()
4885 if (port == 0) { in mvpp2_rx_fifo_init()
4887 MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4890 MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4892 } else if (port == 1) { in mvpp2_rx_fifo_init()
4894 MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4897 MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4901 MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4904 MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4908 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4910 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4923 int port, val; in mvpp2_tx_fifo_init() local
4925 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_tx_fifo_init()
4926 /* Port 0 supports 10KB TX FIFO */ in mvpp2_tx_fifo_init()
4927 if (port == 0) { in mvpp2_tx_fifo_init()
4934 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
4999 /* Checks for hardware constraints (U-Boot uses only one rxq) */ in mvpp2_init()
5000 if ((rxq_number > priv->max_port_rxqs) || in mvpp2_init()
5002 dev_err(&pdev->dev, "invalid queue size parameter\n"); in mvpp2_init()
5003 return -EINVAL; in mvpp2_init()
5006 if (priv->hw_version == MVPP22) in mvpp2_init()
5015 if (priv->hw_version == MVPP21) { in mvpp2_init()
5017 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); in mvpp2_init()
5019 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); in mvpp2_init()
5022 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); in mvpp2_init()
5024 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); in mvpp2_init()
5028 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(), in mvpp2_init()
5031 if (!priv->aggr_txqs) in mvpp2_init()
5032 return -ENOMEM; in mvpp2_init()
5035 priv->aggr_txqs[i].id = i; in mvpp2_init()
5036 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; in mvpp2_init()
5037 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i], in mvpp2_init()
5047 if (priv->hw_version == MVPP22) in mvpp2_init()
5050 if (priv->hw_version == MVPP21) in mvpp2_init()
5052 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); in mvpp2_init()
5083 smi_reg = readl(priv->mdio_base); in smi_wait_ready()
5084 if (timeout-- == 0) { in smi_wait_ready()
5086 return -EFAULT; in smi_wait_ready()
5094 * mpp2_mdio_read - miiphy_read callback function.
5100 struct mvpp2 *priv = bus->priv; in mpp2_mdio_read()
5107 return -EFAULT; in mpp2_mdio_read()
5112 return -EFAULT; in mpp2_mdio_read()
5117 return -EFAULT; in mpp2_mdio_read()
5125 writel(smi_reg, priv->mdio_base); in mpp2_mdio_read()
5132 smi_reg = readl(priv->mdio_base); in mpp2_mdio_read()
5133 if (timeout-- == 0) { in mpp2_mdio_read()
5135 return -EFAULT; in mpp2_mdio_read()
5143 return readl(priv->mdio_base) & MVPP2_SMI_DATA_MASK; in mpp2_mdio_read()
5147 * mpp2_mdio_write - miiphy_write callback function.
5149 * Returns 0 if write succeed, -EINVAL on bad parameters
5150 * -ETIME on timeout
5155 struct mvpp2 *priv = bus->priv; in mpp2_mdio_write()
5161 return -EFAULT; in mpp2_mdio_write()
5166 return -EFAULT; in mpp2_mdio_write()
5171 return -EFAULT; in mpp2_mdio_write()
5180 writel(smi_reg, priv->mdio_base); in mpp2_mdio_write()
5187 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_recv() local
5198 rxq = port->rxqs[0]; in mvpp2_recv()
5200 /* Get number of received packets and clamp the to-do */ in mvpp2_recv()
5201 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_recv()
5208 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_recv()
5209 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); in mvpp2_recv()
5210 rx_bytes -= MVPP2_MH_SIZE; in mvpp2_recv()
5211 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); in mvpp2_recv()
5213 bm = mvpp2_bm_cookie_build(port, rx_desc); in mvpp2_recv()
5215 bm_pool = &port->priv->bm_pools[pool]; in mvpp2_recv()
5223 mvpp2_rx_error(port, rx_desc); in mvpp2_recv()
5225 mvpp2_pool_refill(port, bm, dma_addr, dma_addr); in mvpp2_recv()
5229 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr); in mvpp2_recv()
5231 netdev_err(port->dev, "failed to refill BM pools\n"); in mvpp2_recv()
5237 mvpp2_rxq_status_update(port, rxq->id, 1, 1); in mvpp2_recv()
5239 /* give packet to stack - skip on first n bytes */ in mvpp2_recv()
5256 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_send() local
5262 txq = port->txqs[0]; in mvpp2_send()
5263 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; in mvpp2_send()
5267 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_send()
5268 mvpp2_txdesc_size_set(port, tx_desc, length); in mvpp2_send()
5269 mvpp2_txdesc_offset_set(port, tx_desc, in mvpp2_send()
5271 mvpp2_txdesc_dma_addr_set(port, tx_desc, in mvpp2_send()
5274 mvpp2_txdesc_cmd_set(port, tx_desc, in mvpp2_send()
5284 mvpp2_aggr_txq_pend_desc_add(port, 1); in mvpp2_send()
5286 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_send()
5294 tx_done = mvpp2_txq_pend_desc_num_get(port, txq); in mvpp2_send()
5303 tx_done = mvpp2_txq_sent_desc_proc(port, txq); in mvpp2_send()
5312 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_start() local
5315 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN); in mvpp2_start()
5318 mvpp2_prs_update_mac_da(port, port->dev_addr); in mvpp2_start()
5320 switch (port->phy_interface) { in mvpp2_start()
5324 mvpp2_port_power_up(port); in mvpp2_start()
5329 mvpp2_open(dev, port); in mvpp2_start()
5336 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_stop() local
5338 mvpp2_stop_dev(port); in mvpp2_stop()
5339 mvpp2_cleanup_rxqs(port); in mvpp2_stop()
5340 mvpp2_cleanup_txqs(port); in mvpp2_stop()
5343 static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port) in mvpp22_smi_phy_addr_cfg() argument
5345 writel(port->phyaddr, port->priv->iface_base + in mvpp22_smi_phy_addr_cfg()
5346 MVPP22_SMI_PHY_ADDR_REG(port->gop_id)); in mvpp22_smi_phy_addr_cfg()
5359 /* Save hw-version */ in mvpp2_base_probe()
5360 priv->hw_version = dev_get_driver_data(dev); in mvpp2_base_probe()
5363 * U-Boot special buffer handling: in mvpp2_base_probe()
5367 * be active. Make this area DMA-safe by disabling the D-cache in mvpp2_base_probe()
5389 if (priv->hw_version == MVPP21) in mvpp2_base_probe()
5405 priv->base = (void *)devfdt_get_addr_index(dev, 0); in mvpp2_base_probe()
5406 if (IS_ERR(priv->base)) in mvpp2_base_probe()
5407 return PTR_ERR(priv->base); in mvpp2_base_probe()
5409 if (priv->hw_version == MVPP21) { in mvpp2_base_probe()
5410 priv->lms_base = (void *)devfdt_get_addr_index(dev, 1); in mvpp2_base_probe()
5411 if (IS_ERR(priv->lms_base)) in mvpp2_base_probe()
5412 return PTR_ERR(priv->lms_base); in mvpp2_base_probe()
5414 priv->mdio_base = priv->lms_base + MVPP21_SMI; in mvpp2_base_probe()
5416 priv->iface_base = (void *)devfdt_get_addr_index(dev, 1); in mvpp2_base_probe()
5417 if (IS_ERR(priv->iface_base)) in mvpp2_base_probe()
5418 return PTR_ERR(priv->iface_base); in mvpp2_base_probe()
5420 priv->mdio_base = priv->iface_base + MVPP22_SMI; in mvpp2_base_probe()
5423 priv->mpcs_base = priv->iface_base + MVPP22_MPCS; in mvpp2_base_probe()
5424 priv->xpcs_base = priv->iface_base + MVPP22_XPCS; in mvpp2_base_probe()
5425 priv->rfu1_base = priv->iface_base + MVPP22_RFU1; in mvpp2_base_probe()
5428 if (priv->hw_version == MVPP21) in mvpp2_base_probe()
5429 priv->max_port_rxqs = 8; in mvpp2_base_probe()
5431 priv->max_port_rxqs = 32; in mvpp2_base_probe()
5437 return -ENOMEM; in mvpp2_base_probe()
5440 bus->read = mpp2_mdio_read; in mvpp2_base_probe()
5441 bus->write = mpp2_mdio_write; in mvpp2_base_probe()
5442 snprintf(bus->name, sizeof(bus->name), dev->name); in mvpp2_base_probe()
5443 bus->priv = (void *)priv; in mvpp2_base_probe()
5444 priv->bus = bus; in mvpp2_base_probe()
5451 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_probe() local
5452 struct mvpp2 *priv = dev_get_priv(dev->parent); in mvpp2_probe()
5456 if (!priv->probe_done) in mvpp2_probe()
5457 err = mvpp2_base_probe(dev->parent); in mvpp2_probe()
5459 port->priv = dev_get_priv(dev->parent); in mvpp2_probe()
5461 err = phy_info_parse(dev, port); in mvpp2_probe()
5466 * We need the port specific io base addresses at this stage, since in mvpp2_probe()
5469 if (priv->hw_version == MVPP21) { in mvpp2_probe()
5472 port->base = (void __iomem *)devfdt_get_addr_index( in mvpp2_probe()
5473 dev->parent, priv_common_regs_num + port->id); in mvpp2_probe()
5474 if (IS_ERR(port->base)) in mvpp2_probe()
5475 return PTR_ERR(port->base); in mvpp2_probe()
5477 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), in mvpp2_probe()
5478 "gop-port-id", -1); in mvpp2_probe()
5479 if (port->id == -1) { in mvpp2_probe()
5480 dev_err(&pdev->dev, "missing gop-port-id value\n"); in mvpp2_probe()
5481 return -EINVAL; in mvpp2_probe()
5484 port->base = priv->iface_base + MVPP22_PORT_BASE + in mvpp2_probe()
5485 port->gop_id * MVPP22_PORT_OFFSET; in mvpp2_probe()
5487 /* Set phy address of the port */ in mvpp2_probe()
5488 if(port->phy_node) in mvpp2_probe()
5489 mvpp22_smi_phy_addr_cfg(port); in mvpp2_probe()
5492 gop_port_init(port); in mvpp2_probe()
5495 if (!priv->probe_done) { in mvpp2_probe()
5499 dev_err(&pdev->dev, "failed to initialize controller\n"); in mvpp2_probe()
5502 priv->num_ports = 0; in mvpp2_probe()
5503 priv->probe_done = 1; in mvpp2_probe()
5506 err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv); in mvpp2_probe()
5510 if (priv->hw_version == MVPP22) { in mvpp2_probe()
5511 priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id, in mvpp2_probe()
5512 port->phy_interface); in mvpp2_probe()
5527 struct mvpp2_port *port = dev_get_priv(dev); in mvpp2_remove() local
5528 struct mvpp2 *priv = port->priv; in mvpp2_remove()
5531 priv->num_ports--; in mvpp2_remove()
5533 if (priv->num_ports) in mvpp2_remove()
5537 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]); in mvpp2_remove()
5566 const void *blob = gd->fdt_blob; in mvpp2_base_bind()
5580 return -ENOENT; in mvpp2_base_bind()
5595 return -ENOMEM; in mvpp2_base_bind()
5597 id = fdtdec_get_int(blob, subnode, "port-id", -1); in mvpp2_base_bind()
5603 return -ENOMEM; in mvpp2_base_bind()
5605 sprintf(name, "mvpp2-%d", id); in mvpp2_base_bind()
5617 .compatible = "marvell,armada-375-pp2",
5621 .compatible = "marvell,armada-7k-pp22",