89 	struct axidma_reg *dmarx;  member
363 	temp = readl(&priv->dmarx->control);  in axiemac_stop()
365 	writel(temp, &priv->dmarx->control);  in axiemac_stop()
443 	writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);  in axi_dma_init()
450 				readl(&priv->dmarx->control))  in axi_dma_init()
479 	temp = readl(&priv->dmarx->control);  in axiemac_start()
481 	writel(temp, &priv->dmarx->control);  in axiemac_start()
484 	axienet_dma_write(&rx_bd, &priv->dmarx->current);  in axiemac_start()
499 	temp = readl(&priv->dmarx->control);  in axiemac_start()
501 	writel(temp, &priv->dmarx->control);  in axiemac_start()
504 	axienet_dma_write(&rx_bd, &priv->dmarx->tail);  in axiemac_start()
578 	status = readl(&priv->dmarx->status);  in isrxready()
581 	writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);  in isrxready()
606 	temp = readl(&priv->dmarx->control);  in axiemac_recv()
608 	writel(temp, &priv->dmarx->control);  in axiemac_recv()
645 	axienet_dma_write(&rx_bd, &priv->dmarx->tail);  in axiemac_free_pkt()
734 	priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);  in axi_emac_ofdata_to_platdata()