1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
38 		out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));  in qe_issue_cmd()
40 		out_be32(&qe_immr->cp.cecdr, cmd_data);  in qe_issue_cmd()
41 		out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |  in qe_issue_cmd()
46 		cecr = in_be32(&qe_immr->cp.cecr);  in qe_issue_cmd()
59 	align_mask = align - 1;  in qe_muram_alloc()
60 	savebase = gd->arch.mp_alloc_base;  in qe_muram_alloc()
62 	off = gd->arch.mp_alloc_base & align_mask;  in qe_muram_alloc()
64 		gd->arch.mp_alloc_base += (align - off);  in qe_muram_alloc()
67 		size += (align - off);  in qe_muram_alloc()
69 	if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) {  in qe_muram_alloc()
70 		gd->arch.mp_alloc_base = savebase;  in qe_muram_alloc()
74 	retloc = gd->arch.mp_alloc_base;  in qe_muram_alloc()
75 	gd->arch.mp_alloc_base += size;  in qe_muram_alloc()
77 	memset((void *)&qe_immr->muram[retloc], 0, size);  in qe_muram_alloc()
87 	return (void *)&qe_immr->muram[offset];  in qe_muram_addr()
96 	p = (volatile sdma_t *)&qe_immr->sdma;  in qe_sdma_init()
99 	out_be32(&p->sdaqr, 0);  in qe_sdma_init()
100 	out_be32(&p->sdaqmr, 0);  in qe_sdma_init()
104 	out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);  in qe_sdma_init()
107 	out_be32(&p->sdsr, 0x03000000);  in qe_sdma_init()
110 	out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));  in qe_sdma_init()
114  * "SNUM Table" chart in the QE Reference Manual. The order is not important,
118 /* Evthreads 16-29 are not supported in MPC8309 */
147 	int	snum = -EBUSY;  in qe_get_snum()
175 	/* Init the QE IMMR base */  in qe_init()
180 	 * Upload microcode to IRAM for those SOCs which do not have ROM in QE.  in qe_init()
185 	out_be32(&qe_immr->iram.iready,QE_IRAM_READY);  in qe_init()
188 	gd->arch.mp_alloc_base = QE_DATAONLY_BASE;  in qe_init()
189 	gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;  in qe_init()
207 	if (mmc_initialize(gd->bd)) {  in u_qe_init()
221 		(void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,  in u_qe_init()
226 		out_be32(&qe_immr->iram.iready, QE_IRAM_READY);  in u_qe_init()
240 	out_be32(&qe_immrr->iram.iready, QE_IRAM_READY);  in u_qe_resume()
255 	out_be32(&qe_immr->cp.cecdr, para_ram_base);  in qe_assign_page()
256 	out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)  in qe_assign_page()
261 		cecr = in_be32(&qe_immr->cp.cecr);  in qe_assign_page()
272    the QE clock, it is one-half of the QE clock), If need the clock source
276 #define BRG_CLK		(gd->arch.brg_clk)
286 		return -EINVAL;  in qe_set_brg()
287 	bp = (uint *)&qe_immr->brg.brgc1;  in qe_set_brg()
296 	*bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;  in qe_set_brg()
315 	if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {  in qe_set_mii_clk_src()
317 		return -EINVAL;  in qe_set_mii_clk_src()
320 	cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);  in qe_set_mii_clk_src()
323 	out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);  in qe_set_mii_clk_src()
332  * Set to 1 if QE firmware has been uploaded, and therefore
338  * Upload a QE microcode
346 	const u32 *code = base + be32_to_cpu(ucode->code_offset);  in qe_upload_microcode()
349 	if (ucode->major || ucode->minor || ucode->revision)  in qe_upload_microcode()
350 		printf("QE: uploading microcode '%s' version %u.%u.%u\n",  in qe_upload_microcode()
351 		       (char *)ucode->id, (u16)ucode->major, (u16)ucode->minor,  in qe_upload_microcode()
352 		       (u16)ucode->revision);  in qe_upload_microcode()
354 		printf("QE: uploading microcode '%s'\n", (char *)ucode->id);  in qe_upload_microcode()
356 	/* Use auto-increment */  in qe_upload_microcode()
357 	out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |  in qe_upload_microcode()
360 	for (i = 0; i < be32_to_cpu(ucode->count); i++)  in qe_upload_microcode()
361 		out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));  in qe_upload_microcode()
365  * Upload a microcode to the I-RAM at a specific address.
367  * See docs/README.qe_firmware for information on QE microcode uploading.
397 		return -EINVAL;  in qe_upload_firmware()
400 	hdr = &firmware->header;  in qe_upload_firmware()
401 	length = be32_to_cpu(hdr->length);  in qe_upload_firmware()
404 	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||  in qe_upload_firmware()
405 	    (hdr->magic[2] != 'F')) {  in qe_upload_firmware()
406 		printf("QE microcode not found\n");  in qe_upload_firmware()
408 		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);  in qe_upload_firmware()
410 		return -EPERM;  in qe_upload_firmware()
414 	if (hdr->version != 1) {  in qe_upload_firmware()
416 		return -EPERM;  in qe_upload_firmware()
420 	if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {  in qe_upload_firmware()
422 		return -EINVAL;  in qe_upload_firmware()
426 	calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);  in qe_upload_firmware()
428 	for (i = 0; i < firmware->count; i++)  in qe_upload_firmware()
435 			be32_to_cpu(firmware->microcode[i].count);  in qe_upload_firmware()
440 		return -EPERM;  in qe_upload_firmware()
448 	if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {  in qe_upload_firmware()
450 		return -EIO;  in qe_upload_firmware()
454 	 * If the microcode calls for it, split the I-RAM.  in qe_upload_firmware()
456 	if (!firmware->split) {  in qe_upload_firmware()
457 		out_be16(&qe_immr->cp.cercr,  in qe_upload_firmware()
458 			in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);  in qe_upload_firmware()
461 	if (firmware->soc.model)  in qe_upload_firmware()
463 			firmware->id, be16_to_cpu(firmware->soc.model),  in qe_upload_firmware()
464 			firmware->soc.major, firmware->soc.minor);  in qe_upload_firmware()
466 		printf("Firmware '%s'\n", firmware->id);  in qe_upload_firmware()
469 	 * The QE only supports one microcode per RISC, so clear out all the  in qe_upload_firmware()
473 	strncpy(qe_firmware_info.id, (char *)firmware->id, 62);  in qe_upload_firmware()
474 	qe_firmware_info.extended_modes = firmware->extended_modes;  in qe_upload_firmware()
475 	memcpy(qe_firmware_info.vtraps, firmware->vtraps,  in qe_upload_firmware()
476 		sizeof(firmware->vtraps));  in qe_upload_firmware()
480 	for (i = 0; i < firmware->count; i++) {  in qe_upload_firmware()
481 		const struct qe_microcode *ucode = &firmware->microcode[i];  in qe_upload_firmware()
484 		if (ucode->code_offset)  in qe_upload_firmware()
489 			u32 trap = be32_to_cpu(ucode->traps[j]);  in qe_upload_firmware()
492 				out_be32(&qe_immr->rsp[i].tibcr[j], trap);  in qe_upload_firmware()
496 		out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));  in qe_upload_firmware()
504  * Upload a microcode to the I-RAM at a specific address.
506  * See docs/README.qe_firmware for information on QE microcode uploading.
536 		return -EINVAL;  in u_qe_upload_firmware()
539 	hdr = &firmware->header;  in u_qe_upload_firmware()
540 	length = be32_to_cpu(hdr->length);  in u_qe_upload_firmware()
543 	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||  in u_qe_upload_firmware()
544 	    (hdr->magic[2] != 'F')) {  in u_qe_upload_firmware()
547 		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);  in u_qe_upload_firmware()
549 		return -EPERM;  in u_qe_upload_firmware()
553 	if (hdr->version != 1) {  in u_qe_upload_firmware()
555 		return -EPERM;  in u_qe_upload_firmware()
559 	if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {  in u_qe_upload_firmware()
561 		return -EINVAL;  in u_qe_upload_firmware()
565 	calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);  in u_qe_upload_firmware()
567 	for (i = 0; i < firmware->count; i++)  in u_qe_upload_firmware()
574 			be32_to_cpu(firmware->microcode[i].count);  in u_qe_upload_firmware()
579 		return -EPERM;  in u_qe_upload_firmware()
587 	if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {  in u_qe_upload_firmware()
589 		return -EIO;  in u_qe_upload_firmware()
593 	 * If the microcode calls for it, split the I-RAM.  in u_qe_upload_firmware()
595 	if (!firmware->split) {  in u_qe_upload_firmware()
596 		out_be16(&qe_immr->cp.cercr,  in u_qe_upload_firmware()
597 			 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);  in u_qe_upload_firmware()
600 	if (firmware->soc.model)  in u_qe_upload_firmware()
602 		       firmware->id, be16_to_cpu(firmware->soc.model),  in u_qe_upload_firmware()
603 		       firmware->soc.major, firmware->soc.minor);  in u_qe_upload_firmware()
605 		printf("Firmware '%s'\n", firmware->id);  in u_qe_upload_firmware()
608 	for (i = 0; i < firmware->count; i++) {  in u_qe_upload_firmware()
609 		const struct qe_microcode *ucode = &firmware->microcode[i];  in u_qe_upload_firmware()
612 		if (ucode->code_offset)  in u_qe_upload_firmware()
617 			u32 trap = be32_to_cpu(ucode->traps[j]);  in u_qe_upload_firmware()
620 				out_be32(&qe_immr->rsp[i].tibcr[j], trap);  in u_qe_upload_firmware()
624 		out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));  in u_qe_upload_firmware()
647 		return -EINVAL;  in u_qe_firmware_resume()
649 	hdr = &firmware->header;  in u_qe_firmware_resume()
652 	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||  in u_qe_firmware_resume()
653 	    (hdr->magic[2] != 'F')) {  in u_qe_firmware_resume()
655 		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);  in u_qe_firmware_resume()
657 		return -EPERM;  in u_qe_firmware_resume()
661 	 * If the microcode calls for it, split the I-RAM.  in u_qe_firmware_resume()
663 	if (!firmware->split) {  in u_qe_firmware_resume()
664 		out_be16(&qe_immrr->cp.cercr,  in u_qe_firmware_resume()
665 			 in_be16(&qe_immrr->cp.cercr) | QE_CP_CERCR_CIR);  in u_qe_firmware_resume()
669 	for (i = 0; i < firmware->count; i++) {  in u_qe_firmware_resume()
670 		const struct qe_microcode *ucode = &firmware->microcode[i];  in u_qe_firmware_resume()
673 		if (!ucode->code_offset)  in u_qe_firmware_resume()
676 		code = (const void *)firmware + be32_to_cpu(ucode->code_offset);  in u_qe_firmware_resume()
678 		/* Use auto-increment */  in u_qe_firmware_resume()
679 		out_be32(&qe_immrr->iram.iadd, be32_to_cpu(ucode->iram_offset) |  in u_qe_firmware_resume()
682 		for (i = 0; i < be32_to_cpu(ucode->count); i++)  in u_qe_firmware_resume()
683 			out_be32(&qe_immrr->iram.idata, be32_to_cpu(code[i]));  in u_qe_firmware_resume()
687 			u32 trap = be32_to_cpu(ucode->traps[j]);  in u_qe_firmware_resume()
690 				out_be32(&qe_immrr->rsp[i].tibcr[j], trap);  in u_qe_firmware_resume()
694 		out_be32(&qe_immrr->rsp[i].eccr, be32_to_cpu(ucode->eccr));  in u_qe_firmware_resume()
718 			return -EINVAL;  in qe_cmd()
730 			if (length != be32_to_cpu(firmware->header.length)) {  in qe_cmd()
732 				return -EINVAL;  in qe_cmd()
743 	qe, 4, 0, qe_cmd,
745 	"fw <addr> [<length>] - Upload firmware binary at address <addr> to "
746 		"the QE,\n"