37 	struct rk3288_sdram_pctl_timing pctl_timing;  member
237 	mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |  in memory_init()
238 		DDR3_MR0_CL(params->pctl_timing.tcl) |  in memory_init()
241 	mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);  in memory_init()
451 	struct rk3288_sdram_pctl_timing *pctl_timing = &params->pctl_timing;  in pctl_calc_timings()  local
463 	pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);  in pctl_calc_timings()
464 	pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);  in pctl_calc_timings()
466 	pctl_timing->tinit = 200;                 /* 200 usec                */  in pctl_calc_timings()
467 	pctl_timing->trsth = 500;                 /* 500 usec                */  in pctl_calc_timings()
468 	pctl_timing->trefi = 78;                  /* 7.8usec = 78 * 100ns    */  in pctl_calc_timings()
469 	params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);  in pctl_calc_timings()
472 		pctl_timing->tcl = 6;  in pctl_calc_timings()
473 		pctl_timing->tcwl = 10;  in pctl_calc_timings()
475 		pctl_timing->tcl = 8;  in pctl_calc_timings()
476 		pctl_timing->tcwl = 6;  in pctl_calc_timings()
478 		pctl_timing->tcl = 10;  in pctl_calc_timings()
479 		pctl_timing->tcwl = 7;  in pctl_calc_timings()
481 		pctl_timing->tcl = 11;  in pctl_calc_timings()
482 		pctl_timing->tcwl = 8;  in pctl_calc_timings()
485 	pctl_timing->tmrd = 4;                    /* 4 tCK (all speed bins)  */  in pctl_calc_timings()
486 	pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */  in pctl_calc_timings()
487 	pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));  in pctl_calc_timings()
493 	pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;  in pctl_calc_timings()
494 	pctl_timing->tal = 0;  in pctl_calc_timings()
495 	pctl_timing->tras = ps_to_tCK(35000, freq);  in pctl_calc_timings()
496 	pctl_timing->trc = ps_to_tCK(48750, freq);  in pctl_calc_timings()
497 	pctl_timing->trcd = ps_to_tCK(13750, freq);  in pctl_calc_timings()
498 	pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));  in pctl_calc_timings()
499 	pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));  in pctl_calc_timings()
500 	pctl_timing->twr = ps_to_tCK(15000, freq);  in pctl_calc_timings()
502 	if (pctl_timing->twr > 8)  in pctl_calc_timings()
503 		pctl_timing->twr = (pctl_timing->twr + 1) & ~1;  in pctl_calc_timings()
504 	pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));  in pctl_calc_timings()
505 	pctl_timing->texsr = 512;                 /* tEXSR(max) is tDLLLK    */  in pctl_calc_timings()
506 	pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));  in pctl_calc_timings()
507 	pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));  in pctl_calc_timings()
508 	pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));  in pctl_calc_timings()
509 	pctl_timing->tzqcsi = 10000;               /* as used by Rockchip    */  in pctl_calc_timings()
510 	pctl_timing->tdqs = 1;                     /* fixed for DDR3         */  in pctl_calc_timings()
511 	pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));  in pctl_calc_timings()
512 	pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));  in pctl_calc_timings()
513 	pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));  in pctl_calc_timings()
514 	pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));  in pctl_calc_timings()
515 	pctl_timing->trstl = ns_to_tCK(100, freq);  in pctl_calc_timings()
516 	pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq));   /* tZQoper */  in pctl_calc_timings()
517 	pctl_timing->tmrr = 0;  in pctl_calc_timings()
518 	pctl_timing->tckesr = pctl_timing->tcke + 1;  /* JESD-79: tCKE + 1tCK */  in pctl_calc_timings()
519 	pctl_timing->tdpd = 0;    /* RK3368 TRM: "allowed values for DDR3: 0" */  in pctl_calc_timings()
529 	if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {  in pctl_calc_timings()
531 		pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);  in pctl_calc_timings()
533 	} else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {  in pctl_calc_timings()
535 	} else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {  in pctl_calc_timings()
549 	params->pctl_timing.trefi |= BIT(31);   /* see PCTL_TREFI */  in pctl_cfg()
550 	copy_to_reg(&pctl->togcnt1u, &params->pctl_timing.togcnt1u,  in pctl_cfg()
551 		    sizeof(params->pctl_timing));  in pctl_cfg()
559 	writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);  in pctl_cfg()
560 	writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);  in pctl_cfg()
830 		      params->pctl_timing.tcl,  in setup_sdram()
831 		      params->pctl_timing.tal,  in setup_sdram()
832 		      params->pctl_timing.tcwl);  in setup_sdram()