Lines Matching refs:publ
29 struct rk3288_ddr_publ *publ; member
121 struct rk3288_ddr_publ *publ, in phy_pctrl_reset() argument
128 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
130 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
133 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
135 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
144 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, in phy_dll_bypass_set() argument
151 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
153 setbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
154 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
156 setbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
159 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
161 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
162 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
164 clrbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
168 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
258 struct rk3288_ddr_publ *publ = chan->publ; in phy_cfg() local
266 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()
272 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); in phy_cfg()
275 &publ->ptr[1]); in phy_cfg()
278 &publ->ptr[2]); in phy_cfg()
282 clrbits_le32(&publ->pgcr, 0x1f); in phy_cfg()
283 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
290 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
294 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
298 static void phy_init(struct rk3288_ddr_publ *publ) in phy_init() argument
300 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init()
303 while ((readl(&publ->pgsr) & in phy_init()
325 static void memory_init(struct rk3288_ddr_publ *publ, in memory_init() argument
328 setbits_le32(&publ->pir, in memory_init()
333 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) in memory_init()
338 static void move_to_config_state(struct rk3288_ddr_publ *publ, in move_to_config_state() argument
353 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_config_state()
380 struct rk3288_ddr_publ *publ = chan->publ; in set_bandwidth_ratio() local
388 clrbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
389 clrbits_le32(&publ->datx8[3].dxgcr, 1); in set_bandwidth_ratio()
391 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
392 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
398 setbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
399 setbits_le32(&publ->datx8[3].dxgcr, 1); in set_bandwidth_ratio()
402 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
403 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
405 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
406 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
408 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
409 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
422 struct rk3288_ddr_publ *publ = chan->publ; in data_training() local
429 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
436 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
439 setbits_le32(&publ->pir, in data_training()
444 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) in data_training()
447 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) in data_training()
451 while ((readl(&publ->datx8[2].dxgsr[0]) in data_training()
454 while ((readl(&publ->datx8[3].dxgsr[0]) in data_training()
458 if (readl(&publ->pgsr) & in data_training()
469 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
479 struct rk3288_ddr_publ *publ = chan->publ; in move_to_access_state() local
496 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_access_state()
521 struct rk3288_ddr_publ *publ = chan->publ; in dram_cfg_rbc() local
524 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, in dram_cfg_rbc()
527 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); in dram_cfg_rbc()
570 struct rk3288_ddr_publ *publ = chan->publ; in sdram_rank_bw_detect() local
576 reg = readl(&publ->datx8[0].dxgsr[0]); in sdram_rank_bw_detect()
586 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_rank_bw_detect()
590 reg = readl(&publ->datx8[2].dxgsr[0]); in sdram_rank_bw_detect()
632 struct rk3288_ddr_publ *publ = chan->publ; in sdram_col_row_detect() local
654 move_to_config_state(publ, pctl); in sdram_col_row_detect()
731 struct rk3288_ddr_publ *publ = chan->publ; in sdram_init() local
733 phy_pctrl_reset(dram->cru, publ, channel); in sdram_init()
734 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); in sdram_init()
742 phy_init(publ); in sdram_init()
748 memory_init(publ, sdram_params->base.dramtype); in sdram_init()
749 move_to_config_state(publ, pctl); in sdram_init()
762 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_init()
769 writel(zqcr, &publ->zq1cr[0]); in sdram_init()
770 writel(zqcr, &publ->zq0cr[0]); in sdram_init()
901 priv->chan[0].publ = regmap_get_range(plat->map, 1); in rk3188_dmc_probe()