109 	clrbits_le32(&ddr_phy->ddrphy_reg[0],  in phy_pctrl_reset()
112 	setbits_le32(&ddr_phy->ddrphy_reg[0],  in phy_pctrl_reset()
115 	setbits_le32(&ddr_phy->ddrphy_reg[0],  in phy_pctrl_reset()
125 	setbits_le32(&ddr_phy->ddrphy_reg[0x13], 0x10);  in phy_dll_bypass_set()
126 	setbits_le32(&ddr_phy->ddrphy_reg[0x26], 0x10);  in phy_dll_bypass_set()
127 	setbits_le32(&ddr_phy->ddrphy_reg[0x36], 0x10);  in phy_dll_bypass_set()
128 	setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x10);  in phy_dll_bypass_set()
129 	setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x10);  in phy_dll_bypass_set()
131 	clrbits_le32(&ddr_phy->ddrphy_reg[0x14], 0x8);  in phy_dll_bypass_set()
132 	clrbits_le32(&ddr_phy->ddrphy_reg[0x27], 0x8);  in phy_dll_bypass_set()
133 	clrbits_le32(&ddr_phy->ddrphy_reg[0x37], 0x8);  in phy_dll_bypass_set()
134 	clrbits_le32(&ddr_phy->ddrphy_reg[0x47], 0x8);  in phy_dll_bypass_set()
135 	clrbits_le32(&ddr_phy->ddrphy_reg[0x57], 0x8);  in phy_dll_bypass_set()
138 		setbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f);  in phy_dll_bypass_set()
140 		clrbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f);  in phy_dll_bypass_set()
147 	writel(tmp, &ddr_phy->ddrphy_reg[0x28]);  in phy_dll_bypass_set()
148 	writel(tmp, &ddr_phy->ddrphy_reg[0x38]);  in phy_dll_bypass_set()
149 	writel(tmp, &ddr_phy->ddrphy_reg[0x48]);  in phy_dll_bypass_set()
150 	writel(tmp, &ddr_phy->ddrphy_reg[0x58]);  in phy_dll_bypass_set()
235 	u32 bw = (readl(&ddr_phy->ddrphy_reg[0]) >> 4) & 0xf;  in data_training()
242 	clrsetbits_le32(&ddr_phy->ddrphy_reg[2], 0x30,  in data_training()
244 	setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START);  in data_training()
247 	ret = readl(&ddr_phy->ddrphy_reg[0xff]);  in data_training()
249 	clrbits_le32(&ddr_phy->ddrphy_reg[2],  in data_training()
369 	clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2);  in phy_softreset()
371 	setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2);  in phy_softreset()
373 	setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3);  in phy_softreset()
386 		clrbits_le32(&ddr_phy->ddrphy_reg[0], 0xc << 4);  in set_bw()
388 		clrbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8);  in set_bw()
389 		clrbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8);  in set_bw()
392 		setbits_le32(&ddr_phy->ddrphy_reg[0], 0xf << 4);  in set_bw()
395 		setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8);  in set_bw()
396 		setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8);  in set_bw()
486 		writel(PHY_DDR3 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]);  in phy_cfg()
489 		writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]);  in phy_cfg()
492 		writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]);  in phy_cfg()
496 	writel(phy_timing->cl_al, &ddr_phy->ddrphy_reg[0xb]);  in phy_cfg()
497 	writel(pctl_timing->tcwl, &ddr_phy->ddrphy_reg[0xc]);  in phy_cfg()
507 	writel(cmd_drv, &ddr_phy->ddrphy_reg[0x11]);  in phy_cfg()
508 	clrsetbits_le32(&ddr_phy->ddrphy_reg[0x12], (0x1f << 3), cmd_drv << 3);  in phy_cfg()
509 	writel(clk_drv, &ddr_phy->ddrphy_reg[0x16]);  in phy_cfg()
510 	writel(clk_drv, &ddr_phy->ddrphy_reg[0x18]);  in phy_cfg()
512 	writel(dqs_drv, &ddr_phy->ddrphy_reg[0x20]);  in phy_cfg()
513 	writel(dqs_drv, &ddr_phy->ddrphy_reg[0x2f]);  in phy_cfg()
514 	writel(dqs_drv, &ddr_phy->ddrphy_reg[0x30]);  in phy_cfg()
515 	writel(dqs_drv, &ddr_phy->ddrphy_reg[0x3f]);  in phy_cfg()
516 	writel(dqs_drv, &ddr_phy->ddrphy_reg[0x40]);  in phy_cfg()
517 	writel(dqs_drv, &ddr_phy->ddrphy_reg[0x4f]);  in phy_cfg()
518 	writel(dqs_drv, &ddr_phy->ddrphy_reg[0x50]);  in phy_cfg()
519 	writel(dqs_drv, &ddr_phy->ddrphy_reg[0x5f]);  in phy_cfg()
521 	writel(dqs_odt, &ddr_phy->ddrphy_reg[0x21]);  in phy_cfg()
522 	writel(dqs_odt, &ddr_phy->ddrphy_reg[0x2e]);  in phy_cfg()
523 	writel(dqs_odt, &ddr_phy->ddrphy_reg[0x31]);  in phy_cfg()
524 	writel(dqs_odt, &ddr_phy->ddrphy_reg[0x3e]);  in phy_cfg()
525 	writel(dqs_odt, &ddr_phy->ddrphy_reg[0x41]);  in phy_cfg()
526 	writel(dqs_odt, &ddr_phy->ddrphy_reg[0x4e]);  in phy_cfg()
527 	writel(dqs_odt, &ddr_phy->ddrphy_reg[0x51]);  in phy_cfg()
528 	writel(dqs_odt, &ddr_phy->ddrphy_reg[0x5e]);  in phy_cfg()