Lines Matching refs:publ
31 struct rk3288_ddr_publ *publ; member
120 struct rk3288_ddr_publ *publ, in phy_pctrl_reset() argument
127 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
129 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
132 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
134 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
143 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, in phy_dll_bypass_set() argument
150 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
152 setbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
153 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
155 setbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
158 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
160 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
161 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
163 clrbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
167 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
292 struct rk3288_ddr_publ *publ = chan->publ; in phy_cfg() local
300 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()
309 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); in phy_cfg()
312 &publ->ptr[1]); in phy_cfg()
315 &publ->ptr[2]); in phy_cfg()
319 clrsetbits_le32(&publ->pgcr, 0x1F, in phy_cfg()
325 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
327 clrsetbits_le32(&publ->dxccr, in phy_cfg()
331 tmp = readl(&publ->dtpr[1]); in phy_cfg()
334 clrsetbits_le32(&publ->dsgcr, in phy_cfg()
340 clrbits_le32(&publ->pgcr, 0x1f); in phy_cfg()
341 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
348 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
352 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
356 static void phy_init(struct rk3288_ddr_publ *publ) in phy_init() argument
358 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init()
361 while ((readl(&publ->pgsr) & in phy_init()
383 static void memory_init(struct rk3288_ddr_publ *publ, in memory_init() argument
386 setbits_le32(&publ->pir, in memory_init()
391 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) in memory_init()
396 static void move_to_config_state(struct rk3288_ddr_publ *publ, in move_to_config_state() argument
411 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_config_state()
438 struct rk3288_ddr_publ *publ = chan->publ; in set_bandwidth_ratio() local
446 clrbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
447 clrbits_le32(&publ->datx8[3].dxgcr, 1); in set_bandwidth_ratio()
449 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
450 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
456 setbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
457 setbits_le32(&publ->datx8[3].dxgcr, 1); in set_bandwidth_ratio()
460 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
461 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
463 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
464 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
466 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
467 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
480 struct rk3288_ddr_publ *publ = chan->publ; in data_training() local
487 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
494 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
497 setbits_le32(&publ->pir, in data_training()
502 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) in data_training()
505 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) in data_training()
509 while ((readl(&publ->datx8[2].dxgsr[0]) in data_training()
512 while ((readl(&publ->datx8[3].dxgsr[0]) in data_training()
516 if (readl(&publ->pgsr) & in data_training()
527 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
537 struct rk3288_ddr_publ *publ = chan->publ; in move_to_access_state() local
554 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_access_state()
578 struct rk3288_ddr_publ *publ = chan->publ; in dram_cfg_rbc() local
581 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, in dram_cfg_rbc()
584 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); in dram_cfg_rbc()
623 struct rk3288_ddr_publ *publ = chan->publ; in sdram_rank_bw_detect() local
626 reg = readl(&publ->datx8[0].dxgsr[0]); in sdram_rank_bw_detect()
639 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_rank_bw_detect()
643 reg = readl(&publ->datx8[2].dxgsr[0]); in sdram_rank_bw_detect()
677 struct rk3288_ddr_publ *publ = chan->publ; in sdram_col_row_detect() local
698 move_to_config_state(publ, pctl); in sdram_col_row_detect()
807 struct rk3288_ddr_publ *publ = chan->publ; in sdram_init() local
814 phy_pctrl_reset(dram->cru, publ, channel); in sdram_init()
815 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); in sdram_init()
823 phy_init(publ); in sdram_init()
829 memory_init(publ, sdram_params->base.dramtype); in sdram_init()
830 move_to_config_state(publ, pctl); in sdram_init()
861 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_init()
868 writel(zqcr, &publ->zq1cr[0]); in sdram_init()
869 writel(zqcr, &publ->zq0cr[0]); in sdram_init()
1064 priv->chan[0].publ = regmap_get_range(plat->map, 1); in rk3288_dmc_probe()
1066 priv->chan[1].publ = regmap_get_range(plat->map, 3); in rk3288_dmc_probe()