931 static void dram_all_config(struct dram_info *dram,  in dram_all_config()  argument
961 		ddr_msch_regs = dram->chan[channel].msch;  in dram_all_config()
976 			setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],  in dram_all_config()
980 	writel(sys_reg, &dram->pmugrf->os_reg2);  in dram_all_config()
981 	rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,  in dram_all_config()
987 		&dram->pmucru->pmucru_rstnhold_con[1]);  in dram_all_config()
988 	clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);  in dram_all_config()
991 static int switch_to_phy_index1(struct dram_info *dram,  in switch_to_phy_index1()  argument
1002 			&dram->cic->cic_ctrl0);  in switch_to_phy_index1()
1003 	while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {  in switch_to_phy_index1()
1013 	writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);  in switch_to_phy_index1()
1014 	while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {  in switch_to_phy_index1()
1024 		denali_phy = dram->chan[channel].publ->denali_phy;  in switch_to_phy_index1()
1026 		ret = data_training(&dram->chan[channel], channel,  in switch_to_phy_index1()
1037 static int sdram_init(struct dram_info *dram,  in sdram_init()  argument
1054 		const struct chan_info *chan = &dram->chan[channel];  in sdram_init()
1080 	dram_all_config(dram, sdram_params);  in sdram_init()
1081 	switch_to_phy_index1(dram, sdram_params);  in sdram_init()