148 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)  in dwc3_omap_read_utmi_status()  argument
150 	return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +  in dwc3_omap_read_utmi_status()
151 							omap->utmi_otg_offset);  in dwc3_omap_read_utmi_status()
154 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_utmi_status()  argument
156 	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +  in dwc3_omap_write_utmi_status()
157 					omap->utmi_otg_offset, value);  in dwc3_omap_write_utmi_status()
161 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)  in dwc3_omap_read_irq0_status()  argument
163 	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -  in dwc3_omap_read_irq0_status()
164 						omap->irq0_offset);  in dwc3_omap_read_irq0_status()
167 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_irq0_status()  argument
169 	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -  in dwc3_omap_write_irq0_status()
170 						omap->irq0_offset, value);  in dwc3_omap_write_irq0_status()
174 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)  in dwc3_omap_read_irqmisc_status()  argument
176 	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +  in dwc3_omap_read_irqmisc_status()
177 						omap->irqmisc_offset);  in dwc3_omap_read_irqmisc_status()
180 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_irqmisc_status()  argument
182 	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +  in dwc3_omap_write_irqmisc_status()
183 					omap->irqmisc_offset, value);  in dwc3_omap_write_irqmisc_status()
187 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_irqmisc_set()  argument
189 	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +  in dwc3_omap_write_irqmisc_set()
190 						omap->irqmisc_offset, value);  in dwc3_omap_write_irqmisc_set()
194 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_irq0_set()  argument
196 	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -  in dwc3_omap_write_irq0_set()
197 						omap->irq0_offset, value);  in dwc3_omap_write_irq0_set()
200 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_irqmisc_clr()  argument
202 	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +  in dwc3_omap_write_irqmisc_clr()
203 						omap->irqmisc_offset, value);  in dwc3_omap_write_irqmisc_clr()
206 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_irq0_clr()  argument
208 	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -  in dwc3_omap_write_irq0_clr()
209 						omap->irq0_offset, value);  in dwc3_omap_write_irq0_clr()
212 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,  in dwc3_omap_set_mailbox()  argument
219 		dev_dbg(omap->dev, "ID GND\n");  in dwc3_omap_set_mailbox()
221 		val = dwc3_omap_read_utmi_status(omap);  in dwc3_omap_set_mailbox()
227 		dwc3_omap_write_utmi_status(omap, val);  in dwc3_omap_set_mailbox()
231 		dev_dbg(omap->dev, "VBUS Connect\n");  in dwc3_omap_set_mailbox()
233 		val = dwc3_omap_read_utmi_status(omap);  in dwc3_omap_set_mailbox()
239 		dwc3_omap_write_utmi_status(omap, val);  in dwc3_omap_set_mailbox()
244 		dev_dbg(omap->dev, "VBUS Disconnect\n");  in dwc3_omap_set_mailbox()
246 		val = dwc3_omap_read_utmi_status(omap);  in dwc3_omap_set_mailbox()
252 		dwc3_omap_write_utmi_status(omap, val);  in dwc3_omap_set_mailbox()
256 		dev_dbg(omap->dev, "invalid state\n");  in dwc3_omap_set_mailbox()
262 	struct dwc3_omap	*omap = _omap;  in dwc3_omap_interrupt()  local
265 	reg = dwc3_omap_read_irqmisc_status(omap);  in dwc3_omap_interrupt()
268 		dev_dbg(omap->dev, "DMA Disable was Cleared\n");  in dwc3_omap_interrupt()
269 		omap->dma_status = false;  in dwc3_omap_interrupt()
273 		dev_dbg(omap->dev, "OTG Event\n");  in dwc3_omap_interrupt()
276 		dev_dbg(omap->dev, "DRVVBUS Rise\n");  in dwc3_omap_interrupt()
279 		dev_dbg(omap->dev, "CHRGVBUS Rise\n");  in dwc3_omap_interrupt()
282 		dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");  in dwc3_omap_interrupt()
285 		dev_dbg(omap->dev, "IDPULLUP Rise\n");  in dwc3_omap_interrupt()
288 		dev_dbg(omap->dev, "DRVVBUS Fall\n");  in dwc3_omap_interrupt()
291 		dev_dbg(omap->dev, "CHRGVBUS Fall\n");  in dwc3_omap_interrupt()
294 		dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");  in dwc3_omap_interrupt()
297 		dev_dbg(omap->dev, "IDPULLUP Fall\n");  in dwc3_omap_interrupt()
299 	dwc3_omap_write_irqmisc_status(omap, reg);  in dwc3_omap_interrupt()
301 	reg = dwc3_omap_read_irq0_status(omap);  in dwc3_omap_interrupt()
303 	dwc3_omap_write_irq0_status(omap, reg);  in dwc3_omap_interrupt()
308 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)  in dwc3_omap_enable_irqs()  argument
311 	dwc3_omap_write_irq0_set(omap, USBOTGSS_IRQO_COREIRQ_ST);  in dwc3_omap_enable_irqs()
313 	dwc3_omap_write_irqmisc_set(omap, USBOTGSS_INTERRUPTS);  in dwc3_omap_enable_irqs()
316 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)  in dwc3_omap_disable_irqs()  argument
319 	dwc3_omap_write_irq0_clr(omap, USBOTGSS_IRQO_COREIRQ_ST);  in dwc3_omap_disable_irqs()
321 	dwc3_omap_write_irqmisc_clr(omap, USBOTGSS_INTERRUPTS);  in dwc3_omap_disable_irqs()
324 static void dwc3_omap_map_offset(struct dwc3_omap *omap)  in dwc3_omap_map_offset()  argument
335 	omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;  in dwc3_omap_map_offset()
336 	omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;  in dwc3_omap_map_offset()
337 	omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;  in dwc3_omap_map_offset()
338 	omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;  in dwc3_omap_map_offset()
339 	omap->debug_offset = USBOTGSS_DEBUG_OFFSET;  in dwc3_omap_map_offset()
343 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap, int utmi_mode)  in dwc3_omap_set_utmi_mode()  argument
347 	reg = dwc3_omap_read_utmi_status(omap);  in dwc3_omap_set_utmi_mode()
357 		dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);  in dwc3_omap_set_utmi_mode()
360 	dwc3_omap_write_utmi_status(omap, reg);  in dwc3_omap_set_utmi_mode()
378 	struct dwc3_omap	*omap;  in dwc3_omap_uboot_init()  local
380 	omap = devm_kzalloc((struct udevice *)dev, sizeof(*omap), GFP_KERNEL);  in dwc3_omap_uboot_init()
381 	if (!omap)  in dwc3_omap_uboot_init()
384 	omap->base	= omap_dev->base;  in dwc3_omap_uboot_init()
385 	omap->index	= omap_dev->index;  in dwc3_omap_uboot_init()
387 	dwc3_omap_map_offset(omap);  in dwc3_omap_uboot_init()
388 	dwc3_omap_set_utmi_mode(omap, omap_dev->utmi_mode);  in dwc3_omap_uboot_init()
391 	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);  in dwc3_omap_uboot_init()
392 	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);  in dwc3_omap_uboot_init()
394 	dwc3_omap_set_mailbox(omap, omap_dev->vbus_id_status);  in dwc3_omap_uboot_init()
396 	dwc3_omap_enable_irqs(omap);  in dwc3_omap_uboot_init()
397 	list_add_tail(&omap->list, &dwc3_omap_list);  in dwc3_omap_uboot_init()
415 	struct dwc3_omap *omap = NULL;  in dwc3_omap_uboot_exit()  local
417 	list_for_each_entry(omap, &dwc3_omap_list, list) {  in dwc3_omap_uboot_exit()
418 		if (omap->index != index)  in dwc3_omap_uboot_exit()
421 		dwc3_omap_disable_irqs(omap);  in dwc3_omap_uboot_exit()
422 		list_del(&omap->list);  in dwc3_omap_uboot_exit()
423 		kfree(omap);  in dwc3_omap_uboot_exit()
439 	struct dwc3_omap *omap = NULL;  in dwc3_omap_uboot_interrupt_status()  local
441 	list_for_each_entry(omap, &dwc3_omap_list, list)  in dwc3_omap_uboot_interrupt_status()
442 		if (omap->index == index)  in dwc3_omap_uboot_interrupt_status()
443 			return dwc3_omap_interrupt(-1, omap);  in dwc3_omap_uboot_interrupt_status()