26 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)  in dwc3_set_mode()  argument
28 	clrsetbits_le32(&dwc3_reg->g_ctl,  in dwc3_set_mode()
33 static void dwc3_phy_reset(struct dwc3 *dwc3_reg)  in dwc3_phy_reset()  argument
36 	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);  in dwc3_phy_reset()
39 	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);  in dwc3_phy_reset()
44 	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);  in dwc3_phy_reset()
47 	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);  in dwc3_phy_reset()
50 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)  in dwc3_core_soft_reset()  argument
53 	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);  in dwc3_core_soft_reset()
56 	dwc3_phy_reset(dwc3_reg);  in dwc3_core_soft_reset()
61 	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);  in dwc3_core_soft_reset()
64 int dwc3_core_init(struct dwc3 *dwc3_reg)  in dwc3_core_init()  argument
70 	revision = readl(&dwc3_reg->g_snpsid);  in dwc3_core_init()
77 	dwc3_core_soft_reset(dwc3_reg);  in dwc3_core_init()
79 	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);  in dwc3_core_init()
81 	reg = readl(&dwc3_reg->g_ctl);  in dwc3_core_init()
101 	writel(reg, &dwc3_reg->g_ctl);  in dwc3_core_init()
106 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)  in dwc3_set_fladj()  argument
108 	setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |  in dwc3_set_fladj()
202 	struct dwc3 *dwc3_reg;  in xhci_dwc3_probe()  local
214 	dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);  in xhci_dwc3_probe()
216 	dwc3_core_init(dwc3_reg);  in xhci_dwc3_probe()
223 	dwc3_set_mode(dwc3_reg, dr_mode);  in xhci_dwc3_probe()