Lines Matching refs:csr
40 u16 csr; in write_toggle() local
43 csr = readw(&musbr->txcsr); in write_toggle()
45 if (csr & MUSB_TXCSR_MODE) in write_toggle()
46 csr = MUSB_TXCSR_CLRDATATOG; in write_toggle()
48 csr = 0; in write_toggle()
49 writew(csr, &musbr->txcsr); in write_toggle()
51 csr |= MUSB_TXCSR_H_WR_DATATOGGLE; in write_toggle()
52 writew(csr, &musbr->txcsr); in write_toggle()
53 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT); in write_toggle()
54 writew(csr, &musbr->txcsr); in write_toggle()
58 csr = readw(&musbr->txcsr); in write_toggle()
59 if (csr & MUSB_TXCSR_MODE) in write_toggle()
60 csr = MUSB_RXCSR_CLRDATATOG; in write_toggle()
62 csr = 0; in write_toggle()
63 writew(csr, &musbr->rxcsr); in write_toggle()
65 csr = readw(&musbr->rxcsr); in write_toggle()
66 csr |= MUSB_RXCSR_H_WR_DATATOGGLE; in write_toggle()
67 writew(csr, &musbr->rxcsr); in write_toggle()
68 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE); in write_toggle()
69 writew(csr, &musbr->rxcsr); in write_toggle()
81 u16 csr; in check_stall() local
85 csr = readw(&musbr->txcsr); in check_stall()
86 if (csr & MUSB_CSR0_H_RXSTALL) { in check_stall()
87 csr &= ~MUSB_CSR0_H_RXSTALL; in check_stall()
88 writew(csr, &musbr->txcsr); in check_stall()
93 csr = readw(&musbr->txcsr); in check_stall()
94 if (csr & MUSB_TXCSR_H_RXSTALL) { in check_stall()
95 csr &= ~MUSB_TXCSR_H_RXSTALL; in check_stall()
96 writew(csr, &musbr->txcsr); in check_stall()
100 csr = readw(&musbr->rxcsr); in check_stall()
101 if (csr & MUSB_RXCSR_H_RXSTALL) { in check_stall()
102 csr &= ~MUSB_RXCSR_H_RXSTALL; in check_stall()
103 writew(csr, &musbr->rxcsr); in check_stall()
117 u16 csr; in wait_until_ep0_ready() local
122 csr = readw(&musbr->txcsr); in wait_until_ep0_ready()
123 if (csr & MUSB_CSR0_H_ERROR) { in wait_until_ep0_ready()
124 csr &= ~MUSB_CSR0_H_ERROR; in wait_until_ep0_ready()
125 writew(csr, &musbr->txcsr); in wait_until_ep0_ready()
133 if (!(csr & MUSB_CSR0_TXPKTRDY)) { in wait_until_ep0_ready()
147 if (csr & MUSB_CSR0_RXPKTRDY) in wait_until_ep0_ready()
152 if (!(csr & MUSB_CSR0_H_REQPKT)) { in wait_until_ep0_ready()
180 u16 csr; in wait_until_txep_ready() local
189 csr = readw(&musbr->txcsr); in wait_until_txep_ready()
190 if (csr & MUSB_TXCSR_H_ERROR) { in wait_until_txep_ready()
203 } while (csr & MUSB_TXCSR_TXPKTRDY); in wait_until_txep_ready()
212 u16 csr; in wait_until_rxep_ready() local
221 csr = readw(&musbr->rxcsr); in wait_until_rxep_ready()
222 if (csr & MUSB_RXCSR_H_ERROR) { in wait_until_rxep_ready()
235 } while (!(csr & MUSB_RXCSR_RXPKTRDY)); in wait_until_rxep_ready()
245 u16 csr; in ctrlreq_setup_phase() local
251 csr = readw(&musbr->txcsr); in ctrlreq_setup_phase()
252 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); in ctrlreq_setup_phase()
253 writew(csr, &musbr->txcsr); in ctrlreq_setup_phase()
266 u16 csr; in ctrlreq_in_data_phase() local
279 csr = readw(&musbr->txcsr); in ctrlreq_in_data_phase()
280 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr); in ctrlreq_in_data_phase()
292 csr = readw(&musbr->txcsr); in ctrlreq_in_data_phase()
293 csr &= ~MUSB_CSR0_RXPKTRDY; in ctrlreq_in_data_phase()
294 writew(csr, &musbr->txcsr); in ctrlreq_in_data_phase()
312 u16 csr; in ctrlreq_out_data_phase() local
327 csr = readw(&musbr->txcsr); in ctrlreq_out_data_phase()
329 csr |= MUSB_CSR0_TXPKTRDY; in ctrlreq_out_data_phase()
331 csr |= MUSB_CSR0_H_DIS_PING; in ctrlreq_out_data_phase()
333 writew(csr, &musbr->txcsr); in ctrlreq_out_data_phase()
349 u16 csr; in ctrlreq_out_status_phase() local
353 csr = readw(&musbr->txcsr); in ctrlreq_out_status_phase()
354 csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT); in ctrlreq_out_status_phase()
356 csr |= MUSB_CSR0_H_DIS_PING; in ctrlreq_out_status_phase()
358 writew(csr, &musbr->txcsr); in ctrlreq_out_status_phase()
370 u16 csr; in ctrlreq_in_status_phase() local
374 csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; in ctrlreq_in_status_phase()
376 csr |= MUSB_CSR0_H_DIS_PING; in ctrlreq_in_status_phase()
378 writew(csr, &musbr->txcsr); in ctrlreq_in_status_phase()
382 csr = readw(&musbr->txcsr); in ctrlreq_in_status_phase()
383 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT); in ctrlreq_in_status_phase()
384 writew(csr, &musbr->txcsr); in ctrlreq_in_status_phase()
860 u16 csr; in submit_bulk_msg() local
920 csr = readw(&musbr->txcsr); in submit_bulk_msg()
921 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr); in submit_bulk_msg()
927 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); in submit_bulk_msg()
935 csr = readw(&musbr->txcsr); in submit_bulk_msg()
937 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); in submit_bulk_msg()
955 csr = readw(&musbr->rxcsr); in submit_bulk_msg()
956 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); in submit_bulk_msg()
960 csr = readw(&musbr->rxcsr); in submit_bulk_msg()
962 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); in submit_bulk_msg()
963 csr &= ~MUSB_RXCSR_RXPKTRDY; in submit_bulk_msg()
964 writew(csr, &musbr->rxcsr); in submit_bulk_msg()
974 csr = readw(&musbr->rxcsr); in submit_bulk_msg()
975 csr &= ~MUSB_RXCSR_RXPKTRDY; in submit_bulk_msg()
976 writew(csr, &musbr->rxcsr); in submit_bulk_msg()
981 csr = readw(&musbr->rxcsr); in submit_bulk_msg()
983 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); in submit_bulk_msg()
1067 u16 csr; in submit_int_msg() local
1128 csr = readw(&musbr->rxcsr); in submit_int_msg()
1129 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); in submit_int_msg()
1133 csr = readw(&musbr->rxcsr); in submit_int_msg()
1135 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); in submit_int_msg()
1136 csr &= ~MUSB_RXCSR_RXPKTRDY; in submit_int_msg()
1137 writew(csr, &musbr->rxcsr); in submit_int_msg()
1147 csr = readw(&musbr->rxcsr); in submit_int_msg()
1148 csr &= ~MUSB_RXCSR_RXPKTRDY; in submit_int_msg()
1149 writew(csr, &musbr->rxcsr); in submit_int_msg()
1154 csr = readw(&musbr->rxcsr); in submit_int_msg()
1156 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); in submit_int_msg()