162 static inline void lcdc_write(unsigned int val, u32 *addr)  in lcdc_write()  function
223 		lcdc_write(LCD_CLK_MAIN_RESET,  in lcd_enable_raster()
229 		lcdc_write(0,  in lcd_enable_raster()
236 		lcdc_write(reg | LCD_RASTER_ENABLE,  in lcd_enable_raster()
253 		lcdc_write(reg & ~LCD_RASTER_ENABLE,  in lcd_disable_raster()
267 		lcdc_write(stat, &da8xx_fb_reg_base->stat);  in lcd_disable_raster()
269 		lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);  in lcd_disable_raster()
303 			lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);  in lcd_blit()
308 		lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);  in lcd_blit()
309 		lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);  in lcd_blit()
310 		lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);  in lcd_blit()
311 		lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);  in lcd_blit()
314 		lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);  in lcd_blit()
315 		lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);  in lcd_blit()
316 		lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);  in lcd_blit()
317 		lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);  in lcd_blit()
330 			lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);  in lcd_blit()
333 		lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);  in lcd_blit()
334 		lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);  in lcd_blit()
337 	lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);  in lcd_blit()
338 	lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);  in lcd_blit()
372 	lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);  in lcd_cfg_dma()
385 	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);  in lcd_cfg_ac_bias()
397 	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);  in lcd_cfg_horizontal_sync()
409 	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);  in lcd_cfg_vertical_sync()
448 		lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);  in lcd_cfg_display()
451 	lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);  in lcd_cfg_display()
475 	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);  in lcd_cfg_display()
508 	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);  in lcd_cfg_frame_buffer()
514 	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);  in lcd_cfg_frame_buffer()
520 		lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);  in lcd_cfg_frame_buffer()
534 	lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);  in lcd_cfg_frame_buffer()
633 	lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);  in lcd_reset()
634 	lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);  in lcd_reset()
637 		lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);  in lcd_reset()
639 		lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);  in lcd_reset()
640 		lcdc_write(0, &da8xx_fb_reg_base->clk_reset);  in lcd_reset()
656 	lcdc_write(LCD_CLK_DIVISOR(div) |  in lcd_calc_clk_divider()
660 		lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |  in lcd_calc_clk_divider()
677 		lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |  in lcd_init()
681 		lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &  in lcd_init()
720 	lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |  in lcd_init()
729 	lcdc_write(par->dma_start,  in lcdc_dma_start()
731 	lcdc_write(par->dma_end,  in lcdc_dma_start()
733 	lcdc_write(0,  in lcdc_dma_start()
735 	lcdc_write(0,  in lcdc_dma_start()
748 		lcdc_write(stat, &da8xx_fb_reg_base->stat);  in lcdc_irq_handler_rev01()
761 		lcdc_write(stat, &da8xx_fb_reg_base->stat);  in lcdc_irq_handler_rev01()
766 		lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);  in lcdc_irq_handler_rev01()
772 		lcdc_write(stat, &da8xx_fb_reg_base->stat);  in lcdc_irq_handler_rev01()
777 		lcdc_write(par->dma_start,  in lcdc_irq_handler_rev01()
779 		lcdc_write(par->dma_end,  in lcdc_irq_handler_rev01()
796 		lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);  in lcdc_irq_handler_rev02()
798 		lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);  in lcdc_irq_handler_rev02()
810 		lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);  in lcdc_irq_handler_rev02()
815 		lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);  in lcdc_irq_handler_rev02()
819 		lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);  in lcdc_irq_handler_rev02()
822 		lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);  in lcdc_irq_handler_rev02()
827 		lcdc_write(par->dma_start,  in lcdc_irq_handler_rev02()
829 		lcdc_write(par->dma_end,  in lcdc_irq_handler_rev02()
832 		lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);  in lcdc_irq_handler_rev02()
835 	lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);  in lcdc_irq_handler_rev02()
1011 		lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);  in video_hw_init()
1013 		lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);  in video_hw_init()