Lines Matching refs:pll
31 u32 pll; member
94 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_init()
98 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_init()
101 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_init()
102 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_init()
148 writel(0x30dc5fc0, &phy->pll); in sunxi_dw_hdmi_phy_set()
152 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
155 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
157 setbits_le32(&phy->pll, tmp + 2); in sunxi_dw_hdmi_phy_set()
159 setbits_le32(&phy->pll, 0x3f); in sunxi_dw_hdmi_phy_set()
166 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
170 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
173 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
174 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
180 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
184 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
187 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
188 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
194 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
198 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
201 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
202 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()