Lines Matching refs:sor
48 static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) in tegra_sor_readl() argument
50 return readl((u32 *)sor->base + reg); in tegra_sor_readl()
53 static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg, in tegra_sor_writel() argument
56 writel(val, (u32 *)sor->base + reg); in tegra_sor_writel()
59 static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor, in tegra_sor_write_field() argument
62 u32 reg_val = tegra_sor_readl(sor, reg); in tegra_sor_write_field()
65 tegra_sor_writel(sor, reg, reg_val); in tegra_sor_write_field()
70 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dp_disable_tx_pu() local
72 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dp_disable_tx_pu()
79 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dp_set_pe_vs_pc() local
81 tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg); in tegra_dp_set_pe_vs_pc()
82 tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg); in tegra_dp_set_pe_vs_pc()
84 tegra_sor_write_field(sor, POSTCURSOR(sor->portnum), mask, in tegra_dp_set_pe_vs_pc()
89 static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg, in tegra_dc_sor_poll_register() argument
98 reg_val = tegra_sor_readl(sor, reg); in tegra_dc_sor_poll_register()
112 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_power_state() local
116 orig_val = tegra_sor_readl(sor, PWR); in tegra_dc_sor_set_power_state()
125 tegra_sor_writel(sor, PWR, reg_val); in tegra_dc_sor_set_power_state()
128 if (tegra_dc_sor_poll_register(sor, PWR, in tegra_dc_sor_set_power_state()
143 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_dp_linkctl() local
146 reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); in tegra_dc_sor_set_dp_linkctl()
159 tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val); in tegra_dc_sor_set_dp_linkctl()
163 tegra_sor_writel(sor, DP_TPG, 0x41414141); in tegra_dc_sor_set_dp_linkctl()
169 tegra_sor_writel(sor, DP_TPG, reg_val); in tegra_dc_sor_set_dp_linkctl()
172 tegra_sor_writel(sor, DP_TPG, 0x50505050); in tegra_dc_sor_set_dp_linkctl()
177 static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor, in tegra_dc_sor_enable_lane_sequencer() argument
198 tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val); in tegra_dc_sor_enable_lane_sequencer()
200 if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL, in tegra_dc_sor_enable_lane_sequencer()
214 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_power_dplanes() local
217 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_power_dplanes()
235 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); in tegra_dc_sor_power_dplanes()
239 return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0); in tegra_dc_sor_power_dplanes()
244 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_panel_power() local
247 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_set_panel_power()
254 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); in tegra_dc_sor_set_panel_power()
257 static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div, in tegra_dc_sor_config_pwm() argument
260 tegra_sor_writel(sor, PWM_DIV, pwm_div); in tegra_dc_sor_config_pwm()
261 tegra_sor_writel(sor, PWM_CTL, in tegra_dc_sor_config_pwm()
265 if (tegra_dc_sor_poll_register(sor, PWM_CTL, in tegra_dc_sor_config_pwm()
276 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_dp_mode() local
282 reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum)); in tegra_dc_sor_set_dp_mode()
298 tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val); in tegra_dc_sor_set_dp_mode()
301 tegra_sor_write_field(sor, DP_AUDIO_HBLANK_SYMBOLS, in tegra_dc_sor_set_dp_mode()
305 tegra_sor_write_field(sor, DP_AUDIO_VBLANK_SYMBOLS, in tegra_dc_sor_set_dp_mode()
310 static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor) in tegra_dc_sor_super_update() argument
312 tegra_sor_writel(sor, SUPER_STATE0, 0); in tegra_dc_sor_super_update()
313 tegra_sor_writel(sor, SUPER_STATE0, 1); in tegra_dc_sor_super_update()
314 tegra_sor_writel(sor, SUPER_STATE0, 0); in tegra_dc_sor_super_update()
317 static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor) in tegra_dc_sor_update() argument
319 tegra_sor_writel(sor, STATE0, 0); in tegra_dc_sor_update()
320 tegra_sor_writel(sor, STATE0, 1); in tegra_dc_sor_update()
321 tegra_sor_writel(sor, STATE0, 0); in tegra_dc_sor_update()
324 static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up) in tegra_dc_sor_io_set_dpd() argument
327 void *pmc_base = sor->pmc_base; in tegra_dc_sor_io_set_dpd()
372 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_internal_panel() local
375 reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum)); in tegra_dc_sor_set_internal_panel()
383 tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val); in tegra_dc_sor_set_internal_panel()
389 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_read_link_config() local
392 reg_val = tegra_sor_readl(sor, CLK_CNTRL); in tegra_dc_sor_read_link_config()
395 reg_val = tegra_sor_readl(sor, in tegra_dc_sor_read_link_config()
396 DP_LINKCTL(sor->portnum)); in tegra_dc_sor_read_link_config()
418 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_link_bandwidth() local
420 tegra_sor_write_field(sor, CLK_CNTRL, in tegra_dc_sor_set_link_bandwidth()
427 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_lane_count() local
430 reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); in tegra_dc_sor_set_lane_count()
449 tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val); in tegra_dc_sor_set_lane_count()
465 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_power_up() local
469 if (sor->power_is_up) in tegra_dc_sor_power_up()
476 reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_power_up()
486 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
493 tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */ in tegra_dc_sor_power_up()
496 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dc_sor_power_up()
501 ret = tegra_dc_sor_io_set_dpd(sor, 1); in tegra_dc_sor_power_up()
507 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
513 tegra_sor_write_field(sor, PLL0, in tegra_dc_sor_power_up()
518 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
524 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_power_up()
528 sor->power_is_up = 1; in tegra_dc_sor_power_up()
534 static void dump_sor_reg(struct tegra_dc_sor_data *sor) in dump_sor_reg() argument
537 #a, a, tegra_sor_readl(sor, a)); in dump_sor_reg()
607 static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor, in tegra_dc_sor_config_panel() argument
630 tegra_sor_writel(sor, STATE1, reg_val); in tegra_dc_sor_config_panel()
641 tegra_sor_writel(sor, NV_HEAD_STATE1(head_num), in tegra_dc_sor_config_panel()
647 tegra_sor_writel(sor, NV_HEAD_STATE2(head_num), in tegra_dc_sor_config_panel()
653 tegra_sor_writel(sor, NV_HEAD_STATE3(head_num), in tegra_dc_sor_config_panel()
659 tegra_sor_writel(sor, NV_HEAD_STATE4(head_num), in tegra_dc_sor_config_panel()
664 tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1); in tegra_dc_sor_config_panel()
666 tegra_sor_write_field(sor, CSTM, in tegra_dc_sor_config_panel()
673 tegra_dc_sor_config_pwm(sor, 1024, 1024); in tegra_dc_sor_config_panel()
692 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_enable_dp() local
695 tegra_sor_write_field(sor, CLK_CNTRL, in tegra_dc_sor_enable_dp()
699 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_enable_dp()
704 tegra_sor_write_field(sor, PLL3, in tegra_dc_sor_enable_dp()
707 tegra_sor_writel(sor, PLL0, in tegra_dc_sor_enable_dp()
713 tegra_sor_write_field(sor, PLL2, in tegra_dc_sor_enable_dp()
720 tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | in tegra_dc_sor_enable_dp()
723 if (tegra_dc_sor_poll_register(sor, PLL2, in tegra_dc_sor_enable_dp()
731 tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK | in tegra_dc_sor_enable_dp()
758 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_attach() local
767 tegra_dc_sor_config_panel(sor, 0, link_cfg, timing); in tegra_dc_sor_attach()
776 reg_val = tegra_sor_readl(sor, TEST); in tegra_dc_sor_attach()
780 tegra_sor_writel(sor, SUPER_STATE1, in tegra_dc_sor_attach()
793 tegra_dc_sor_update(sor); in tegra_dc_sor_attach()
794 tegra_sor_writel(sor, SUPER_STATE1, in tegra_dc_sor_attach()
796 tegra_sor_writel(sor, SUPER_STATE1, in tegra_dc_sor_attach()
800 tegra_dc_sor_super_update(sor); in tegra_dc_sor_attach()
810 if (tegra_dc_sor_poll_register(sor, TEST, in tegra_dc_sor_attach()
822 dump_sor_reg(sor); in tegra_dc_sor_attach()
832 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_lane_parm() local
834 tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), in tegra_dc_sor_set_lane_parm()
836 tegra_sor_writel(sor, PR(sor->portnum), in tegra_dc_sor_set_lane_parm()
838 tegra_sor_writel(sor, POSTCURSOR(sor->portnum), in tegra_dc_sor_set_lane_parm()
840 tegra_sor_writel(sor, LVDS, 0); in tegra_dc_sor_set_lane_parm()
845 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dc_sor_set_lane_parm()
852 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0); in tegra_dc_sor_set_lane_parm()
855 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0); in tegra_dc_sor_set_lane_parm()
861 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_set_voltage_swing() local
879 tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), drive_current); in tegra_dc_sor_set_voltage_swing()
880 tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis); in tegra_dc_sor_set_voltage_swing()
888 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_power_down_unused_lanes() local
917 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl); in tegra_dc_sor_power_down_unused_lanes()
919 err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0); in tegra_dc_sor_power_down_unused_lanes()
929 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_sor_precharge_lanes() local
948 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_sor_precharge_lanes()
952 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_sor_precharge_lanes()
969 struct tegra_dc_sor_data *sor = dev_get_priv(dev); in tegra_dc_sor_detach() local
980 tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | in tegra_dc_sor_detach()
983 tegra_dc_sor_super_update(sor); in tegra_dc_sor_detach()
987 if (tegra_dc_sor_poll_register(sor, TEST, in tegra_dc_sor_detach()
996 tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | in tegra_dc_sor_detach()