Lines Matching defs:ddr4_spd_eeprom_s
291 struct ddr4_spd_eeprom_s { struct
293 uint8_t info_size_crc; /* 0 # bytes */
294 uint8_t spd_rev; /* 1 Total # bytes of SPD */
295 uint8_t mem_type; /* 2 Key Byte / mem type */
296 uint8_t module_type; /* 3 Key Byte / Module Type */
297 uint8_t density_banks; /* 4 Density and Banks */
298 uint8_t addressing; /* 5 Addressing */
299 uint8_t package_type; /* 6 Package type */
300 uint8_t opt_feature; /* 7 Optional features */
301 uint8_t thermal_ref; /* 8 Thermal and refresh */
302 uint8_t oth_opt_features; /* 9 Other optional features */
303 uint8_t res_10; /* 10 Reserved */
304 uint8_t module_vdd; /* 11 Module nominal voltage */
305 uint8_t organization; /* 12 Module Organization */
306 uint8_t bus_width; /* 13 Module Memory Bus Width */
307 uint8_t therm_sensor; /* 14 Module Thermal Sensor */
308 uint8_t ext_type; /* 15 Extended module type */
309 uint8_t res_16;
310 uint8_t timebases; /* 17 MTb and FTB */
311 uint8_t tck_min; /* 18 tCKAVGmin */
312 uint8_t tck_max; /* 19 TCKAVGmax */
313 uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */
314 uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */
315 uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */
316 uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */
317 uint8_t taa_min; /* 24 Min CAS Latency Time */
318 uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */
319 uint8_t trp_min; /* 26 Min Row Precharge Delay Time */
320 uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
321 uint8_t tras_min_lsb; /* 28 tRASmin, lsb */
322 uint8_t trc_min_lsb; /* 29 tRCmin, lsb */
323 uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */
324 uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */
325 uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */
326 uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */
327 uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */
328 uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */
329 uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */
330 uint8_t tfaw_min; /* 37 tFAW, lsb */
331 uint8_t trrds_min; /* 38 tRRD_Smin, MTB */
332 uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */
333 uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */
334 uint8_t res_41[60-41]; /* 41 Rserved */
335 uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
336 uint8_t res_78[117-78]; /* 78~116, Reserved */
337 int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */
338 int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */
339 int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */
340 int8_t fine_trc_min; /* 120 Fine offset for tRCmin */
341 int8_t fine_trp_min; /* 121 Fine offset for tRPmin */
342 int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */
343 int8_t fine_taa_min; /* 123 Fine offset for tAAmin */
344 int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */
345 int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */
347 uint8_t crc[2]; /* 126-127 SPD CRC */
350 union {
479 } mod_section;
481 uint8_t res_256[320-256]; /* 256~319 Reserved */
505 unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd); argument