Lines Matching +full:- +full:qe
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
21 #define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
23 /* QE threads SNUM
35 /* QE RISC allocation
48 /* QE CECR commands for UCC fast.
74 /* QE CECR Sub Block Code - sub block code of QE command.
108 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
117 /* QE ASSIGN PAGE command
177 /* QE CMXGCR register
182 /* QE CMXUCR registers
186 /* QE BRG configuration register
193 /* QE SDMA registers
219 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
223 /* I-RAM */
228 /* Structure that defines QE firmware binary files.
238 u8 id[62]; /* Null-terminated identifier string */
239 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
251 u8 id[32]; /* Null-terminated identifier */
254 u32 iram_offset;/* Offset into I-RAM for the code */
255 u32 count; /* Number of 32-bit words of the code */