Lines Matching +full:- +full:qe
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * QUICC Engine (QE) Internal Memory Map.
4 * The Internal Memory Map for devices with QE on them. This
5 * is the superset of all QE devices (8360, etc.).
7 * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc.
38 /* QE I-RAM */
40 u32 iadd; /* I-RAM Address Register */
41 u32 idata; /* I-RAM Data Register */
47 /* QE Interrupt Controller */
72 u32 cecr; /* QE command register */
73 u32 ceccr; /* QE controller configuration register */
74 u32 cecdr; /* QE command data register */
76 u16 ceter; /* QE timer event register */
78 u16 cetmr; /* QE timers mask register */
79 u32 cetscr; /* QE time-stamp timer control register */
80 u32 cetsr1; /* QE time-stamp register 1 */
81 u32 cetsr2; /* QE time-stamp register 2 */
83 u32 cevter; /* QE virtual tasks event register */
84 u32 cevtmr; /* QE virtual tasks mask register */
85 u16 cercr; /* QE RAM control register */
88 u16 ceexe1; /* QE external request 1 event register */
90 u16 ceexm1; /* QE external request 1 mask register */
92 u16 ceexe2; /* QE external request 2 event register */
94 u16 ceexm2; /* QE external request 2 mask register */
96 u16 ceexe3; /* QE external request 3 event register */
98 u16 ceexm3; /* QE external request 3 mask register */
100 u16 ceexe4; /* QE external request 4 event register */
102 u16 ceexm4; /* QE external request 4 mask register */
107 /* QE Multiplexer */
121 /* QE Timers */
275 /* QE UCC Slow */
279 u16 upsmr; /* UCCx protocol-specific mode register */
291 u8 res4[0x200 - 0x091];
309 u32 hafdup; /* half-duplex reg. */
325 u8 res3[0x180 - 0x15A];
376 u8 res5[0x200 - 0x1c4];
379 /* QE UCC Fast */
382 u32 upsmr; /* UCCx protocol-specific mode register */
409 u8 res9[0x100 - 0x091];
413 /* QE UCC */
417 u8 res2[0x200 - 0x091];
523 * the QE Developer's Handbook.
553 u8 res4[0x100-0xf8];
557 qe_iram_t iram; /* I-RAM */
560 qe_mux_t qmx; /* QE Multiplexer */
561 qe_timers_t qet; /* QE Timers */
587 u8 res16[0x8000]; /* 0x108000 - 0x110000 */