Lines Matching refs:vform
347 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1() argument
348 dst.ClearForWrite(vform); in ld1()
349 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld1()
350 dst.ReadUintFromMem(vform, i, addr); in ld1()
351 addr += LaneSizeInBytesFromFormat(vform); in ld1()
355 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, int index, in ld1() argument
357 dst.ReadUintFromMem(vform, index, addr); in ld1()
360 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1r() argument
361 dst.ClearForWrite(vform); in ld1r()
362 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld1r()
363 dst.ReadUintFromMem(vform, i, addr); in ld1r()
367 void Simulator::ld2(VectorFormat vform, LogicVRegister dst1, in ld2() argument
369 dst1.ClearForWrite(vform); in ld2()
370 dst2.ClearForWrite(vform); in ld2()
371 int esize = LaneSizeInBytesFromFormat(vform); in ld2()
373 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld2()
374 dst1.ReadUintFromMem(vform, i, addr1); in ld2()
375 dst2.ReadUintFromMem(vform, i, addr2); in ld2()
381 void Simulator::ld2(VectorFormat vform, LogicVRegister dst1, in ld2() argument
383 dst1.ClearForWrite(vform); in ld2()
384 dst2.ClearForWrite(vform); in ld2()
385 uint64_t addr2 = addr1 + LaneSizeInBytesFromFormat(vform); in ld2()
386 dst1.ReadUintFromMem(vform, index, addr1); in ld2()
387 dst2.ReadUintFromMem(vform, index, addr2); in ld2()
390 void Simulator::ld2r(VectorFormat vform, LogicVRegister dst1, in ld2r() argument
392 dst1.ClearForWrite(vform); in ld2r()
393 dst2.ClearForWrite(vform); in ld2r()
394 uint64_t addr2 = addr + LaneSizeInBytesFromFormat(vform); in ld2r()
395 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld2r()
396 dst1.ReadUintFromMem(vform, i, addr); in ld2r()
397 dst2.ReadUintFromMem(vform, i, addr2); in ld2r()
401 void Simulator::ld3(VectorFormat vform, LogicVRegister dst1, in ld3() argument
403 dst1.ClearForWrite(vform); in ld3()
404 dst2.ClearForWrite(vform); in ld3()
405 dst3.ClearForWrite(vform); in ld3()
406 int esize = LaneSizeInBytesFromFormat(vform); in ld3()
409 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld3()
410 dst1.ReadUintFromMem(vform, i, addr1); in ld3()
411 dst2.ReadUintFromMem(vform, i, addr2); in ld3()
412 dst3.ReadUintFromMem(vform, i, addr3); in ld3()
419 void Simulator::ld3(VectorFormat vform, LogicVRegister dst1, in ld3() argument
422 dst1.ClearForWrite(vform); in ld3()
423 dst2.ClearForWrite(vform); in ld3()
424 dst3.ClearForWrite(vform); in ld3()
425 uint64_t addr2 = addr1 + LaneSizeInBytesFromFormat(vform); in ld3()
426 uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform); in ld3()
427 dst1.ReadUintFromMem(vform, index, addr1); in ld3()
428 dst2.ReadUintFromMem(vform, index, addr2); in ld3()
429 dst3.ReadUintFromMem(vform, index, addr3); in ld3()
432 void Simulator::ld3r(VectorFormat vform, LogicVRegister dst1, in ld3r() argument
434 dst1.ClearForWrite(vform); in ld3r()
435 dst2.ClearForWrite(vform); in ld3r()
436 dst3.ClearForWrite(vform); in ld3r()
437 uint64_t addr2 = addr + LaneSizeInBytesFromFormat(vform); in ld3r()
438 uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform); in ld3r()
439 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld3r()
440 dst1.ReadUintFromMem(vform, i, addr); in ld3r()
441 dst2.ReadUintFromMem(vform, i, addr2); in ld3r()
442 dst3.ReadUintFromMem(vform, i, addr3); in ld3r()
446 void Simulator::ld4(VectorFormat vform, LogicVRegister dst1, in ld4() argument
449 dst1.ClearForWrite(vform); in ld4()
450 dst2.ClearForWrite(vform); in ld4()
451 dst3.ClearForWrite(vform); in ld4()
452 dst4.ClearForWrite(vform); in ld4()
453 int esize = LaneSizeInBytesFromFormat(vform); in ld4()
457 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld4()
458 dst1.ReadUintFromMem(vform, i, addr1); in ld4()
459 dst2.ReadUintFromMem(vform, i, addr2); in ld4()
460 dst3.ReadUintFromMem(vform, i, addr3); in ld4()
461 dst4.ReadUintFromMem(vform, i, addr4); in ld4()
469 void Simulator::ld4(VectorFormat vform, LogicVRegister dst1, in ld4() argument
472 dst1.ClearForWrite(vform); in ld4()
473 dst2.ClearForWrite(vform); in ld4()
474 dst3.ClearForWrite(vform); in ld4()
475 dst4.ClearForWrite(vform); in ld4()
476 uint64_t addr2 = addr1 + LaneSizeInBytesFromFormat(vform); in ld4()
477 uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform); in ld4()
478 uint64_t addr4 = addr3 + LaneSizeInBytesFromFormat(vform); in ld4()
479 dst1.ReadUintFromMem(vform, index, addr1); in ld4()
480 dst2.ReadUintFromMem(vform, index, addr2); in ld4()
481 dst3.ReadUintFromMem(vform, index, addr3); in ld4()
482 dst4.ReadUintFromMem(vform, index, addr4); in ld4()
485 void Simulator::ld4r(VectorFormat vform, LogicVRegister dst1, in ld4r() argument
488 dst1.ClearForWrite(vform); in ld4r()
489 dst2.ClearForWrite(vform); in ld4r()
490 dst3.ClearForWrite(vform); in ld4r()
491 dst4.ClearForWrite(vform); in ld4r()
492 uint64_t addr2 = addr + LaneSizeInBytesFromFormat(vform); in ld4r()
493 uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform); in ld4r()
494 uint64_t addr4 = addr3 + LaneSizeInBytesFromFormat(vform); in ld4r()
495 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld4r()
496 dst1.ReadUintFromMem(vform, i, addr); in ld4r()
497 dst2.ReadUintFromMem(vform, i, addr2); in ld4r()
498 dst3.ReadUintFromMem(vform, i, addr3); in ld4r()
499 dst4.ReadUintFromMem(vform, i, addr4); in ld4r()
503 void Simulator::st1(VectorFormat vform, LogicVRegister src, uint64_t addr) { in st1() argument
504 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in st1()
505 src.WriteUintToMem(vform, i, addr); in st1()
506 addr += LaneSizeInBytesFromFormat(vform); in st1()
510 void Simulator::st1(VectorFormat vform, LogicVRegister src, int index, in st1() argument
512 src.WriteUintToMem(vform, index, addr); in st1()
515 void Simulator::st2(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, in st2() argument
517 int esize = LaneSizeInBytesFromFormat(vform); in st2()
519 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in st2()
520 dst.WriteUintToMem(vform, i, addr); in st2()
521 dst2.WriteUintToMem(vform, i, addr2); in st2()
527 void Simulator::st2(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, in st2() argument
529 int esize = LaneSizeInBytesFromFormat(vform); in st2()
530 dst.WriteUintToMem(vform, index, addr); in st2()
531 dst2.WriteUintToMem(vform, index, addr + 1 * esize); in st2()
534 void Simulator::st3(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, in st3() argument
536 int esize = LaneSizeInBytesFromFormat(vform); in st3()
539 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in st3()
540 dst.WriteUintToMem(vform, i, addr); in st3()
541 dst2.WriteUintToMem(vform, i, addr2); in st3()
542 dst3.WriteUintToMem(vform, i, addr3); in st3()
549 void Simulator::st3(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, in st3() argument
551 int esize = LaneSizeInBytesFromFormat(vform); in st3()
552 dst.WriteUintToMem(vform, index, addr); in st3()
553 dst2.WriteUintToMem(vform, index, addr + 1 * esize); in st3()
554 dst3.WriteUintToMem(vform, index, addr + 2 * esize); in st3()
557 void Simulator::st4(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, in st4() argument
559 int esize = LaneSizeInBytesFromFormat(vform); in st4()
563 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in st4()
564 dst.WriteUintToMem(vform, i, addr); in st4()
565 dst2.WriteUintToMem(vform, i, addr2); in st4()
566 dst3.WriteUintToMem(vform, i, addr3); in st4()
567 dst4.WriteUintToMem(vform, i, addr4); in st4()
575 void Simulator::st4(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, in st4() argument
578 int esize = LaneSizeInBytesFromFormat(vform); in st4()
579 dst.WriteUintToMem(vform, index, addr); in st4()
580 dst2.WriteUintToMem(vform, index, addr + 1 * esize); in st4()
581 dst3.WriteUintToMem(vform, index, addr + 2 * esize); in st4()
582 dst4.WriteUintToMem(vform, index, addr + 3 * esize); in st4()
585 LogicVRegister Simulator::cmp(VectorFormat vform, LogicVRegister dst, in cmp() argument
588 dst.ClearForWrite(vform); in cmp()
589 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in cmp()
590 int64_t sa = src1.Int(vform, i); in cmp()
591 int64_t sb = src2.Int(vform, i); in cmp()
592 uint64_t ua = src1.Uint(vform, i); in cmp()
593 uint64_t ub = src2.Uint(vform, i); in cmp()
620 dst.SetUint(vform, i, result ? MaxUintFromFormat(vform) : 0); in cmp()
625 LogicVRegister Simulator::cmp(VectorFormat vform, LogicVRegister dst, in cmp() argument
629 LogicVRegister imm_reg = dup_immediate(vform, temp, imm); in cmp()
630 return cmp(vform, dst, src1, imm_reg, cond); in cmp()
633 LogicVRegister Simulator::cmptst(VectorFormat vform, LogicVRegister dst, in cmptst() argument
636 dst.ClearForWrite(vform); in cmptst()
637 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in cmptst()
638 uint64_t ua = src1.Uint(vform, i); in cmptst()
639 uint64_t ub = src2.Uint(vform, i); in cmptst()
640 dst.SetUint(vform, i, ((ua & ub) != 0) ? MaxUintFromFormat(vform) : 0); in cmptst()
645 LogicVRegister Simulator::add(VectorFormat vform, LogicVRegister dst, in add() argument
648 int lane_size = LaneSizeInBitsFromFormat(vform); in add()
649 dst.ClearForWrite(vform); in add()
650 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in add()
652 uint64_t ua = src1.UintLeftJustified(vform, i); in add()
653 uint64_t ub = src2.UintLeftJustified(vform, i); in add()
669 dst.SetInt(vform, i, ur >> (64 - lane_size)); in add()
674 LogicVRegister Simulator::addp(VectorFormat vform, LogicVRegister dst, in addp() argument
678 uzp1(vform, temp1, src1, src2); in addp()
679 uzp2(vform, temp2, src1, src2); in addp()
680 add(vform, dst, temp1, temp2); in addp()
684 LogicVRegister Simulator::mla(VectorFormat vform, LogicVRegister dst, in mla() argument
688 mul(vform, temp, src1, src2); in mla()
689 add(vform, dst, dst, temp); in mla()
693 LogicVRegister Simulator::mls(VectorFormat vform, LogicVRegister dst, in mls() argument
697 mul(vform, temp, src1, src2); in mls()
698 sub(vform, dst, dst, temp); in mls()
702 LogicVRegister Simulator::mul(VectorFormat vform, LogicVRegister dst, in mul() argument
705 dst.ClearForWrite(vform); in mul()
706 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in mul()
707 dst.SetUint(vform, i, src1.Uint(vform, i) * src2.Uint(vform, i)); in mul()
712 LogicVRegister Simulator::mul(VectorFormat vform, LogicVRegister dst, in mul() argument
716 VectorFormat indexform = VectorFormatFillQ(vform); in mul()
717 return mul(vform, dst, src1, dup_element(indexform, temp, src2, index)); in mul()
720 LogicVRegister Simulator::mla(VectorFormat vform, LogicVRegister dst, in mla() argument
724 VectorFormat indexform = VectorFormatFillQ(vform); in mla()
725 return mla(vform, dst, src1, dup_element(indexform, temp, src2, index)); in mla()
728 LogicVRegister Simulator::mls(VectorFormat vform, LogicVRegister dst, in mls() argument
732 VectorFormat indexform = VectorFormatFillQ(vform); in mls()
733 return mls(vform, dst, src1, dup_element(indexform, temp, src2, index)); in mls()
736 LogicVRegister Simulator::smull(VectorFormat vform, LogicVRegister dst, in smull() argument
741 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in smull()
742 return smull(vform, dst, src1, dup_element(indexform, temp, src2, index)); in smull()
745 LogicVRegister Simulator::smull2(VectorFormat vform, LogicVRegister dst, in smull2() argument
750 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in smull2()
751 return smull2(vform, dst, src1, dup_element(indexform, temp, src2, index)); in smull2()
754 LogicVRegister Simulator::umull(VectorFormat vform, LogicVRegister dst, in umull() argument
759 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in umull()
760 return umull(vform, dst, src1, dup_element(indexform, temp, src2, index)); in umull()
763 LogicVRegister Simulator::umull2(VectorFormat vform, LogicVRegister dst, in umull2() argument
768 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in umull2()
769 return umull2(vform, dst, src1, dup_element(indexform, temp, src2, index)); in umull2()
772 LogicVRegister Simulator::smlal(VectorFormat vform, LogicVRegister dst, in smlal() argument
777 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in smlal()
778 return smlal(vform, dst, src1, dup_element(indexform, temp, src2, index)); in smlal()
781 LogicVRegister Simulator::smlal2(VectorFormat vform, LogicVRegister dst, in smlal2() argument
786 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in smlal2()
787 return smlal2(vform, dst, src1, dup_element(indexform, temp, src2, index)); in smlal2()
790 LogicVRegister Simulator::umlal(VectorFormat vform, LogicVRegister dst, in umlal() argument
795 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in umlal()
796 return umlal(vform, dst, src1, dup_element(indexform, temp, src2, index)); in umlal()
799 LogicVRegister Simulator::umlal2(VectorFormat vform, LogicVRegister dst, in umlal2() argument
804 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in umlal2()
805 return umlal2(vform, dst, src1, dup_element(indexform, temp, src2, index)); in umlal2()
808 LogicVRegister Simulator::smlsl(VectorFormat vform, LogicVRegister dst, in smlsl() argument
813 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in smlsl()
814 return smlsl(vform, dst, src1, dup_element(indexform, temp, src2, index)); in smlsl()
817 LogicVRegister Simulator::smlsl2(VectorFormat vform, LogicVRegister dst, in smlsl2() argument
822 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in smlsl2()
823 return smlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index)); in smlsl2()
826 LogicVRegister Simulator::umlsl(VectorFormat vform, LogicVRegister dst, in umlsl() argument
831 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in umlsl()
832 return umlsl(vform, dst, src1, dup_element(indexform, temp, src2, index)); in umlsl()
835 LogicVRegister Simulator::umlsl2(VectorFormat vform, LogicVRegister dst, in umlsl2() argument
840 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in umlsl2()
841 return umlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index)); in umlsl2()
844 LogicVRegister Simulator::sqdmull(VectorFormat vform, LogicVRegister dst, in sqdmull() argument
849 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in sqdmull()
850 return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmull()
853 LogicVRegister Simulator::sqdmull2(VectorFormat vform, LogicVRegister dst, in sqdmull2() argument
858 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in sqdmull2()
859 return sqdmull2(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmull2()
862 LogicVRegister Simulator::sqdmlal(VectorFormat vform, LogicVRegister dst, in sqdmlal() argument
867 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in sqdmlal()
868 return sqdmlal(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmlal()
871 LogicVRegister Simulator::sqdmlal2(VectorFormat vform, LogicVRegister dst, in sqdmlal2() argument
876 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in sqdmlal2()
877 return sqdmlal2(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmlal2()
880 LogicVRegister Simulator::sqdmlsl(VectorFormat vform, LogicVRegister dst, in sqdmlsl() argument
885 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in sqdmlsl()
886 return sqdmlsl(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmlsl()
889 LogicVRegister Simulator::sqdmlsl2(VectorFormat vform, LogicVRegister dst, in sqdmlsl2() argument
894 VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); in sqdmlsl2()
895 return sqdmlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmlsl2()
898 LogicVRegister Simulator::sqdmulh(VectorFormat vform, LogicVRegister dst, in sqdmulh() argument
902 VectorFormat indexform = VectorFormatFillQ(vform); in sqdmulh()
903 return sqdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmulh()
906 LogicVRegister Simulator::sqrdmulh(VectorFormat vform, LogicVRegister dst, in sqrdmulh() argument
910 VectorFormat indexform = VectorFormatFillQ(vform); in sqrdmulh()
911 return sqrdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqrdmulh()
925 LogicVRegister Simulator::pmul(VectorFormat vform, LogicVRegister dst, in pmul() argument
928 dst.ClearForWrite(vform); in pmul()
929 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in pmul()
930 dst.SetUint(vform, i, in pmul()
931 PolynomialMult(src1.Uint(vform, i), src2.Uint(vform, i))); in pmul()
936 LogicVRegister Simulator::pmull(VectorFormat vform, LogicVRegister dst, in pmull() argument
939 VectorFormat vform_src = VectorFormatHalfWidth(vform); in pmull()
940 dst.ClearForWrite(vform); in pmull()
941 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in pmull()
943 vform, i, in pmull()
949 LogicVRegister Simulator::pmull2(VectorFormat vform, LogicVRegister dst, in pmull2() argument
952 VectorFormat vform_src = VectorFormatHalfWidthDoubleLanes(vform); in pmull2()
953 dst.ClearForWrite(vform); in pmull2()
954 int lane_count = LaneCountFromFormat(vform); in pmull2()
956 dst.SetUint(vform, i, in pmull2()
963 LogicVRegister Simulator::sub(VectorFormat vform, LogicVRegister dst, in sub() argument
966 int lane_size = LaneSizeInBitsFromFormat(vform); in sub()
967 dst.ClearForWrite(vform); in sub()
968 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in sub()
970 uint64_t ua = src1.UintLeftJustified(vform, i); in sub()
971 uint64_t ub = src2.UintLeftJustified(vform, i); in sub()
987 dst.SetInt(vform, i, ur >> (64 - lane_size)); in sub()
992 LogicVRegister Simulator::and_(VectorFormat vform, LogicVRegister dst, in and_() argument
995 dst.ClearForWrite(vform); in and_()
996 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in and_()
997 dst.SetUint(vform, i, src1.Uint(vform, i) & src2.Uint(vform, i)); in and_()
1002 LogicVRegister Simulator::orr(VectorFormat vform, LogicVRegister dst, in orr() argument
1005 dst.ClearForWrite(vform); in orr()
1006 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in orr()
1007 dst.SetUint(vform, i, src1.Uint(vform, i) | src2.Uint(vform, i)); in orr()
1012 LogicVRegister Simulator::orn(VectorFormat vform, LogicVRegister dst, in orn() argument
1015 dst.ClearForWrite(vform); in orn()
1016 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in orn()
1017 dst.SetUint(vform, i, src1.Uint(vform, i) | ~src2.Uint(vform, i)); in orn()
1022 LogicVRegister Simulator::eor(VectorFormat vform, LogicVRegister dst, in eor() argument
1025 dst.ClearForWrite(vform); in eor()
1026 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in eor()
1027 dst.SetUint(vform, i, src1.Uint(vform, i) ^ src2.Uint(vform, i)); in eor()
1032 LogicVRegister Simulator::bic(VectorFormat vform, LogicVRegister dst, in bic() argument
1035 dst.ClearForWrite(vform); in bic()
1036 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in bic()
1037 dst.SetUint(vform, i, src1.Uint(vform, i) & ~src2.Uint(vform, i)); in bic()
1042 LogicVRegister Simulator::bic(VectorFormat vform, LogicVRegister dst, in bic() argument
1045 int laneCount = LaneCountFromFormat(vform); in bic()
1047 result[i] = src.Uint(vform, i) & ~imm; in bic()
1049 dst.SetUintArray(vform, result); in bic()
1053 LogicVRegister Simulator::bif(VectorFormat vform, LogicVRegister dst, in bif() argument
1056 dst.ClearForWrite(vform); in bif()
1057 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in bif()
1058 uint64_t operand1 = dst.Uint(vform, i); in bif()
1059 uint64_t operand2 = ~src2.Uint(vform, i); in bif()
1060 uint64_t operand3 = src1.Uint(vform, i); in bif()
1062 dst.SetUint(vform, i, result); in bif()
1067 LogicVRegister Simulator::bit(VectorFormat vform, LogicVRegister dst, in bit() argument
1070 dst.ClearForWrite(vform); in bit()
1071 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in bit()
1072 uint64_t operand1 = dst.Uint(vform, i); in bit()
1073 uint64_t operand2 = src2.Uint(vform, i); in bit()
1074 uint64_t operand3 = src1.Uint(vform, i); in bit()
1076 dst.SetUint(vform, i, result); in bit()
1081 LogicVRegister Simulator::bsl(VectorFormat vform, LogicVRegister dst, in bsl() argument
1084 dst.ClearForWrite(vform); in bsl()
1085 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in bsl()
1086 uint64_t operand1 = src2.Uint(vform, i); in bsl()
1087 uint64_t operand2 = dst.Uint(vform, i); in bsl()
1088 uint64_t operand3 = src1.Uint(vform, i); in bsl()
1090 dst.SetUint(vform, i, result); in bsl()
1095 LogicVRegister Simulator::SMinMax(VectorFormat vform, LogicVRegister dst, in SMinMax() argument
1098 dst.ClearForWrite(vform); in SMinMax()
1099 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in SMinMax()
1100 int64_t src1_val = src1.Int(vform, i); in SMinMax()
1101 int64_t src2_val = src2.Int(vform, i); in SMinMax()
1108 dst.SetInt(vform, i, dst_val); in SMinMax()
1113 LogicVRegister Simulator::smax(VectorFormat vform, LogicVRegister dst, in smax() argument
1116 return SMinMax(vform, dst, src1, src2, true); in smax()
1119 LogicVRegister Simulator::smin(VectorFormat vform, LogicVRegister dst, in smin() argument
1122 return SMinMax(vform, dst, src1, src2, false); in smin()
1125 LogicVRegister Simulator::SMinMaxP(VectorFormat vform, LogicVRegister dst, in SMinMaxP() argument
1128 int lanes = LaneCountFromFormat(vform); in SMinMaxP()
1133 int64_t first_val = src->Int(vform, i); in SMinMaxP()
1134 int64_t second_val = src->Int(vform, i + 1); in SMinMaxP()
1146 dst.SetIntArray(vform, result); in SMinMaxP()
1150 LogicVRegister Simulator::smaxp(VectorFormat vform, LogicVRegister dst, in smaxp() argument
1153 return SMinMaxP(vform, dst, src1, src2, true); in smaxp()
1156 LogicVRegister Simulator::sminp(VectorFormat vform, LogicVRegister dst, in sminp() argument
1159 return SMinMaxP(vform, dst, src1, src2, false); in sminp()
1162 LogicVRegister Simulator::addp(VectorFormat vform, LogicVRegister dst, in addp() argument
1164 DCHECK_EQ(vform, kFormatD); in addp()
1167 dst.ClearForWrite(vform); in addp()
1168 dst.SetUint(vform, 0, dst_val); in addp()
1172 LogicVRegister Simulator::addv(VectorFormat vform, LogicVRegister dst, in addv() argument
1175 ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform)); in addv()
1178 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in addv()
1179 dst_val += src.Int(vform, i); in addv()
1187 LogicVRegister Simulator::saddlv(VectorFormat vform, LogicVRegister dst, in saddlv() argument
1190 ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform) * 2); in saddlv()
1193 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in saddlv()
1194 dst_val += src.Int(vform, i); in saddlv()
1202 LogicVRegister Simulator::uaddlv(VectorFormat vform, LogicVRegister dst, in uaddlv() argument
1205 ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform) * 2); in uaddlv()
1208 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in uaddlv()
1209 dst_val += src.Uint(vform, i); in uaddlv()
1217 LogicVRegister Simulator::SMinMaxV(VectorFormat vform, LogicVRegister dst, in SMinMaxV() argument
1220 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in SMinMaxV()
1221 int64_t src_val = src.Int(vform, i); in SMinMaxV()
1228 dst.ClearForWrite(ScalarFormatFromFormat(vform)); in SMinMaxV()
1229 dst.SetInt(vform, 0, dst_val); in SMinMaxV()
1233 LogicVRegister Simulator::smaxv(VectorFormat vform, LogicVRegister dst, in smaxv() argument
1235 SMinMaxV(vform, dst, src, true); in smaxv()
1239 LogicVRegister Simulator::sminv(VectorFormat vform, LogicVRegister dst, in sminv() argument
1241 SMinMaxV(vform, dst, src, false); in sminv()
1245 LogicVRegister Simulator::UMinMax(VectorFormat vform, LogicVRegister dst, in UMinMax() argument
1248 dst.ClearForWrite(vform); in UMinMax()
1249 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in UMinMax()
1250 uint64_t src1_val = src1.Uint(vform, i); in UMinMax()
1251 uint64_t src2_val = src2.Uint(vform, i); in UMinMax()
1258 dst.SetUint(vform, i, dst_val); in UMinMax()
1263 LogicVRegister Simulator::umax(VectorFormat vform, LogicVRegister dst, in umax() argument
1266 return UMinMax(vform, dst, src1, src2, true); in umax()
1269 LogicVRegister Simulator::umin(VectorFormat vform, LogicVRegister dst, in umin() argument
1272 return UMinMax(vform, dst, src1, src2, false); in umin()
1275 LogicVRegister Simulator::UMinMaxP(VectorFormat vform, LogicVRegister dst, in UMinMaxP() argument
1278 int lanes = LaneCountFromFormat(vform); in UMinMaxP()
1282 for (int i = 0; i < LaneCountFromFormat(vform); i += 2) { in UMinMaxP()
1283 uint64_t first_val = src->Uint(vform, i); in UMinMaxP()
1284 uint64_t second_val = src->Uint(vform, i + 1); in UMinMaxP()
1296 dst.SetUintArray(vform, result); in UMinMaxP()
1300 LogicVRegister Simulator::umaxp(VectorFormat vform, LogicVRegister dst, in umaxp() argument
1303 return UMinMaxP(vform, dst, src1, src2, true); in umaxp()
1306 LogicVRegister Simulator::uminp(VectorFormat vform, LogicVRegister dst, in uminp() argument
1309 return UMinMaxP(vform, dst, src1, src2, false); in uminp()
1312 LogicVRegister Simulator::UMinMaxV(VectorFormat vform, LogicVRegister dst, in UMinMaxV() argument
1315 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in UMinMaxV()
1316 uint64_t src_val = src.Uint(vform, i); in UMinMaxV()
1323 dst.ClearForWrite(ScalarFormatFromFormat(vform)); in UMinMaxV()
1324 dst.SetUint(vform, 0, dst_val); in UMinMaxV()
1328 LogicVRegister Simulator::umaxv(VectorFormat vform, LogicVRegister dst, in umaxv() argument
1330 UMinMaxV(vform, dst, src, true); in umaxv()
1334 LogicVRegister Simulator::uminv(VectorFormat vform, LogicVRegister dst, in uminv() argument
1336 UMinMaxV(vform, dst, src, false); in uminv()
1340 LogicVRegister Simulator::shl(VectorFormat vform, LogicVRegister dst, in shl() argument
1344 LogicVRegister shiftreg = dup_immediate(vform, temp, shift); in shl()
1345 return ushl(vform, dst, src, shiftreg); in shl()
1348 LogicVRegister Simulator::sshll(VectorFormat vform, LogicVRegister dst, in sshll() argument
1352 LogicVRegister shiftreg = dup_immediate(vform, temp1, shift); in sshll()
1353 LogicVRegister extendedreg = sxtl(vform, temp2, src); in sshll()
1354 return sshl(vform, dst, extendedreg, shiftreg); in sshll()
1357 LogicVRegister Simulator::sshll2(VectorFormat vform, LogicVRegister dst, in sshll2() argument
1361 LogicVRegister shiftreg = dup_immediate(vform, temp1, shift); in sshll2()
1362 LogicVRegister extendedreg = sxtl2(vform, temp2, src); in sshll2()
1363 return sshl(vform, dst, extendedreg, shiftreg); in sshll2()
1366 LogicVRegister Simulator::shll(VectorFormat vform, LogicVRegister dst, in shll() argument
1368 int shift = LaneSizeInBitsFromFormat(vform) / 2; in shll()
1369 return sshll(vform, dst, src, shift); in shll()
1372 LogicVRegister Simulator::shll2(VectorFormat vform, LogicVRegister dst, in shll2() argument
1374 int shift = LaneSizeInBitsFromFormat(vform) / 2; in shll2()
1375 return sshll2(vform, dst, src, shift); in shll2()
1378 LogicVRegister Simulator::ushll(VectorFormat vform, LogicVRegister dst, in ushll() argument
1382 LogicVRegister shiftreg = dup_immediate(vform, temp1, shift); in ushll()
1383 LogicVRegister extendedreg = uxtl(vform, temp2, src); in ushll()
1384 return ushl(vform, dst, extendedreg, shiftreg); in ushll()
1387 LogicVRegister Simulator::ushll2(VectorFormat vform, LogicVRegister dst, in ushll2() argument
1391 LogicVRegister shiftreg = dup_immediate(vform, temp1, shift); in ushll2()
1392 LogicVRegister extendedreg = uxtl2(vform, temp2, src); in ushll2()
1393 return ushl(vform, dst, extendedreg, shiftreg); in ushll2()
1396 LogicVRegister Simulator::sli(VectorFormat vform, LogicVRegister dst, in sli() argument
1398 dst.ClearForWrite(vform); in sli()
1399 int laneCount = LaneCountFromFormat(vform); in sli()
1401 uint64_t src_lane = src.Uint(vform, i); in sli()
1402 uint64_t dst_lane = dst.Uint(vform, i); in sli()
1404 uint64_t mask = MaxUintFromFormat(vform) << shift; in sli()
1405 dst.SetUint(vform, i, (dst_lane & ~mask) | shifted); in sli()
1410 LogicVRegister Simulator::sqshl(VectorFormat vform, LogicVRegister dst, in sqshl() argument
1414 LogicVRegister shiftreg = dup_immediate(vform, temp, shift); in sqshl()
1415 return sshl(vform, dst, src, shiftreg).SignedSaturate(vform); in sqshl()
1418 LogicVRegister Simulator::uqshl(VectorFormat vform, LogicVRegister dst, in uqshl() argument
1422 LogicVRegister shiftreg = dup_immediate(vform, temp, shift); in uqshl()
1423 return ushl(vform, dst, src, shiftreg).UnsignedSaturate(vform); in uqshl()
1426 LogicVRegister Simulator::sqshlu(VectorFormat vform, LogicVRegister dst, in sqshlu() argument
1430 LogicVRegister shiftreg = dup_immediate(vform, temp, shift); in sqshlu()
1431 return sshl(vform, dst, src, shiftreg).UnsignedSaturate(vform); in sqshlu()
1434 LogicVRegister Simulator::sri(VectorFormat vform, LogicVRegister dst, in sri() argument
1436 dst.ClearForWrite(vform); in sri()
1437 int laneCount = LaneCountFromFormat(vform); in sri()
1439 (shift <= static_cast<int>(LaneSizeInBitsFromFormat(vform)))); in sri()
1441 uint64_t src_lane = src.Uint(vform, i); in sri()
1442 uint64_t dst_lane = dst.Uint(vform, i); in sri()
1450 mask = MaxUintFromFormat(vform) >> shift; in sri()
1452 dst.SetUint(vform, i, (dst_lane & ~mask) | shifted); in sri()
1457 LogicVRegister Simulator::ushr(VectorFormat vform, LogicVRegister dst, in ushr() argument
1461 LogicVRegister shiftreg = dup_immediate(vform, temp, -shift); in ushr()
1462 return ushl(vform, dst, src, shiftreg); in ushr()
1465 LogicVRegister Simulator::sshr(VectorFormat vform, LogicVRegister dst, in sshr() argument
1469 LogicVRegister shiftreg = dup_immediate(vform, temp, -shift); in sshr()
1470 return sshl(vform, dst, src, shiftreg); in sshr()
1473 LogicVRegister Simulator::ssra(VectorFormat vform, LogicVRegister dst, in ssra() argument
1476 LogicVRegister shifted_reg = sshr(vform, temp, src, shift); in ssra()
1477 return add(vform, dst, dst, shifted_reg); in ssra()
1480 LogicVRegister Simulator::usra(VectorFormat vform, LogicVRegister dst, in usra() argument
1483 LogicVRegister shifted_reg = ushr(vform, temp, src, shift); in usra()
1484 return add(vform, dst, dst, shifted_reg); in usra()
1487 LogicVRegister Simulator::srsra(VectorFormat vform, LogicVRegister dst, in srsra() argument
1490 LogicVRegister shifted_reg = sshr(vform, temp, src, shift).Round(vform); in srsra()
1491 return add(vform, dst, dst, shifted_reg); in srsra()
1494 LogicVRegister Simulator::ursra(VectorFormat vform, LogicVRegister dst, in ursra() argument
1497 LogicVRegister shifted_reg = ushr(vform, temp, src, shift).Round(vform); in ursra()
1498 return add(vform, dst, dst, shifted_reg); in ursra()
1501 LogicVRegister Simulator::cls(VectorFormat vform, LogicVRegister dst, in cls() argument
1504 int laneSizeInBits = LaneSizeInBitsFromFormat(vform); in cls()
1505 int laneCount = LaneCountFromFormat(vform); in cls()
1507 result[i] = CountLeadingSignBits(src.Int(vform, i), laneSizeInBits); in cls()
1510 dst.SetUintArray(vform, result); in cls()
1514 LogicVRegister Simulator::clz(VectorFormat vform, LogicVRegister dst, in clz() argument
1517 int laneSizeInBits = LaneSizeInBitsFromFormat(vform); in clz()
1518 int laneCount = LaneCountFromFormat(vform); in clz()
1520 result[i] = CountLeadingZeros(src.Uint(vform, i), laneSizeInBits); in clz()
1523 dst.SetUintArray(vform, result); in clz()
1527 LogicVRegister Simulator::cnt(VectorFormat vform, LogicVRegister dst, in cnt() argument
1530 int laneSizeInBits = LaneSizeInBitsFromFormat(vform); in cnt()
1531 int laneCount = LaneCountFromFormat(vform); in cnt()
1533 uint64_t value = src.Uint(vform, i); in cnt()
1541 dst.SetUintArray(vform, result); in cnt()
1545 LogicVRegister Simulator::sshl(VectorFormat vform, LogicVRegister dst, in sshl() argument
1548 dst.ClearForWrite(vform); in sshl()
1549 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in sshl()
1550 int8_t shift_val = src2.Int(vform, i); in sshl()
1551 int64_t lj_src_val = src1.IntLeftJustified(vform, i); in sshl()
1567 int64_t src_val = src1.Int(vform, i); in sshl()
1570 dst.SetInt(vform, i, 0); in sshl()
1573 dst.SetInt(vform, i, src_is_negative ? -1 : 0); in sshl()
1598 dst.SetUint(vform, i, usrc_val); in sshl()
1604 LogicVRegister Simulator::ushl(VectorFormat vform, LogicVRegister dst, in ushl() argument
1607 dst.ClearForWrite(vform); in ushl()
1608 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ushl()
1609 int8_t shift_val = src2.Int(vform, i); in ushl()
1610 uint64_t lj_src_val = src1.UintLeftJustified(vform, i); in ushl()
1617 uint64_t src_val = src1.Uint(vform, i); in ushl()
1619 dst.SetUint(vform, i, 0); in ushl()
1635 dst.SetUint(vform, i, src_val); in ushl()
1641 LogicVRegister Simulator::neg(VectorFormat vform, LogicVRegister dst, in neg() argument
1643 dst.ClearForWrite(vform); in neg()
1644 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in neg()
1646 int64_t sa = src.Int(vform, i); in neg()
1647 if (sa == MinIntFromFormat(vform)) { in neg()
1650 dst.SetInt(vform, i, (sa == INT64_MIN) ? sa : -sa); in neg()
1655 LogicVRegister Simulator::suqadd(VectorFormat vform, LogicVRegister dst, in suqadd() argument
1657 dst.ClearForWrite(vform); in suqadd()
1658 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in suqadd()
1659 int64_t sa = dst.IntLeftJustified(vform, i); in suqadd()
1660 uint64_t ub = src.UintLeftJustified(vform, i); in suqadd()
1665 dst.SetInt(vform, i, MaxIntFromFormat(vform)); in suqadd()
1667 dst.SetUint(vform, i, dst.Int(vform, i) + src.Uint(vform, i)); in suqadd()
1673 LogicVRegister Simulator::usqadd(VectorFormat vform, LogicVRegister dst, in usqadd() argument
1675 dst.ClearForWrite(vform); in usqadd()
1676 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in usqadd()
1677 uint64_t ua = dst.UintLeftJustified(vform, i); in usqadd()
1678 int64_t sb = src.IntLeftJustified(vform, i); in usqadd()
1682 dst.SetUint(vform, i, MaxUintFromFormat(vform)); // Positive saturation. in usqadd()
1684 dst.SetUint(vform, i, 0); // Negative saturation. in usqadd()
1686 dst.SetUint(vform, i, dst.Uint(vform, i) + src.Int(vform, i)); in usqadd()
1692 LogicVRegister Simulator::abs(VectorFormat vform, LogicVRegister dst, in abs() argument
1694 dst.ClearForWrite(vform); in abs()
1695 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in abs()
1697 int64_t sa = src.Int(vform, i); in abs()
1698 if (sa == MinIntFromFormat(vform)) { in abs()
1702 dst.SetInt(vform, i, (sa == INT64_MIN) ? sa : -sa); in abs()
1704 dst.SetInt(vform, i, sa); in abs()
1810 LogicVRegister Simulator::xtn(VectorFormat vform, LogicVRegister dst, in xtn() argument
1812 return ExtractNarrow(vform, dst, true, src, true); in xtn()
1815 LogicVRegister Simulator::sqxtn(VectorFormat vform, LogicVRegister dst, in sqxtn() argument
1817 return ExtractNarrow(vform, dst, true, src, true).SignedSaturate(vform); in sqxtn()
1820 LogicVRegister Simulator::sqxtun(VectorFormat vform, LogicVRegister dst, in sqxtun() argument
1822 return ExtractNarrow(vform, dst, false, src, true).UnsignedSaturate(vform); in sqxtun()
1825 LogicVRegister Simulator::uqxtn(VectorFormat vform, LogicVRegister dst, in uqxtn() argument
1827 return ExtractNarrow(vform, dst, false, src, false).UnsignedSaturate(vform); in uqxtn()
1830 LogicVRegister Simulator::AbsDiff(VectorFormat vform, LogicVRegister dst, in AbsDiff() argument
1833 dst.ClearForWrite(vform); in AbsDiff()
1834 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in AbsDiff()
1836 int64_t sr = src1.Int(vform, i) - src2.Int(vform, i); in AbsDiff()
1838 dst.SetInt(vform, i, sr); in AbsDiff()
1840 int64_t sr = src1.Uint(vform, i) - src2.Uint(vform, i); in AbsDiff()
1842 dst.SetUint(vform, i, sr); in AbsDiff()
1848 LogicVRegister Simulator::saba(VectorFormat vform, LogicVRegister dst, in saba() argument
1852 dst.ClearForWrite(vform); in saba()
1853 AbsDiff(vform, temp, src1, src2, true); in saba()
1854 add(vform, dst, dst, temp); in saba()
1858 LogicVRegister Simulator::uaba(VectorFormat vform, LogicVRegister dst, in uaba() argument
1862 dst.ClearForWrite(vform); in uaba()
1863 AbsDiff(vform, temp, src1, src2, false); in uaba()
1864 add(vform, dst, dst, temp); in uaba()
1868 LogicVRegister Simulator::not_(VectorFormat vform, LogicVRegister dst, in not_() argument
1870 dst.ClearForWrite(vform); in not_()
1871 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in not_()
1872 dst.SetUint(vform, i, ~src.Uint(vform, i)); in not_()
1877 LogicVRegister Simulator::rbit(VectorFormat vform, LogicVRegister dst, in rbit() argument
1880 int laneCount = LaneCountFromFormat(vform); in rbit()
1881 int laneSizeInBits = LaneSizeInBitsFromFormat(vform); in rbit()
1885 value = src.Uint(vform, i); in rbit()
1894 dst.SetUintArray(vform, result); in rbit()
1898 LogicVRegister Simulator::rev(VectorFormat vform, LogicVRegister dst, in rev() argument
1901 int laneCount = LaneCountFromFormat(vform); in rev()
1902 int laneSize = LaneSizeInBytesFromFormat(vform); in rev()
1906 result[i + lanesPerLoop - 1 - j] = src.Uint(vform, i + j); in rev()
1909 dst.SetUintArray(vform, result); in rev()
1913 LogicVRegister Simulator::rev16(VectorFormat vform, LogicVRegister dst, in rev16() argument
1915 return rev(vform, dst, src, 2); in rev16()
1918 LogicVRegister Simulator::rev32(VectorFormat vform, LogicVRegister dst, in rev32() argument
1920 return rev(vform, dst, src, 4); in rev32()
1923 LogicVRegister Simulator::rev64(VectorFormat vform, LogicVRegister dst, in rev64() argument
1925 return rev(vform, dst, src, 8); in rev64()
1928 LogicVRegister Simulator::addlp(VectorFormat vform, LogicVRegister dst, in addlp() argument
1931 VectorFormat vformsrc = VectorFormatHalfWidthDoubleLanes(vform); in addlp()
1933 DCHECK_LE(LaneCountFromFormat(vform), 8); in addlp()
1936 int lane_count = LaneCountFromFormat(vform); in addlp()
1946 dst.ClearForWrite(vform); in addlp()
1949 result[i] += dst.Uint(vform, i); in addlp()
1951 dst.SetUint(vform, i, result[i]); in addlp()
1957 LogicVRegister Simulator::saddlp(VectorFormat vform, LogicVRegister dst, in saddlp() argument
1959 return addlp(vform, dst, src, true, false); in saddlp()
1962 LogicVRegister Simulator::uaddlp(VectorFormat vform, LogicVRegister dst, in uaddlp() argument
1964 return addlp(vform, dst, src, false, false); in uaddlp()
1967 LogicVRegister Simulator::sadalp(VectorFormat vform, LogicVRegister dst, in sadalp() argument
1969 return addlp(vform, dst, src, true, true); in sadalp()
1972 LogicVRegister Simulator::uadalp(VectorFormat vform, LogicVRegister dst, in uadalp() argument
1974 return addlp(vform, dst, src, false, true); in uadalp()
1977 LogicVRegister Simulator::ext(VectorFormat vform, LogicVRegister dst, in ext() argument
1981 int laneCount = LaneCountFromFormat(vform); in ext()
1983 result[i] = src1.Uint(vform, i + index); in ext()
1986 result[laneCount - index + i] = src2.Uint(vform, i); in ext()
1988 dst.ClearForWrite(vform); in ext()
1990 dst.SetUint(vform, i, result[i]); in ext()
1995 LogicVRegister Simulator::dup_element(VectorFormat vform, LogicVRegister dst, in dup_element() argument
1998 int laneCount = LaneCountFromFormat(vform); in dup_element()
1999 uint64_t value = src.Uint(vform, src_index); in dup_element()
2000 dst.ClearForWrite(vform); in dup_element()
2002 dst.SetUint(vform, i, value); in dup_element()
2007 LogicVRegister Simulator::dup_immediate(VectorFormat vform, LogicVRegister dst, in dup_immediate() argument
2009 int laneCount = LaneCountFromFormat(vform); in dup_immediate()
2010 uint64_t value = imm & MaxUintFromFormat(vform); in dup_immediate()
2011 dst.ClearForWrite(vform); in dup_immediate()
2013 dst.SetUint(vform, i, value); in dup_immediate()
2018 LogicVRegister Simulator::ins_element(VectorFormat vform, LogicVRegister dst, in ins_element() argument
2021 dst.SetUint(vform, dst_index, src.Uint(vform, src_index)); in ins_element()
2025 LogicVRegister Simulator::ins_immediate(VectorFormat vform, LogicVRegister dst, in ins_immediate() argument
2027 uint64_t value = imm & MaxUintFromFormat(vform); in ins_immediate()
2028 dst.SetUint(vform, dst_index, value); in ins_immediate()
2032 LogicVRegister Simulator::movi(VectorFormat vform, LogicVRegister dst, in movi() argument
2034 int laneCount = LaneCountFromFormat(vform); in movi()
2035 dst.ClearForWrite(vform); in movi()
2037 dst.SetUint(vform, i, imm); in movi()
2042 LogicVRegister Simulator::mvni(VectorFormat vform, LogicVRegister dst, in mvni() argument
2044 int laneCount = LaneCountFromFormat(vform); in mvni()
2045 dst.ClearForWrite(vform); in mvni()
2047 dst.SetUint(vform, i, ~imm); in mvni()
2052 LogicVRegister Simulator::orr(VectorFormat vform, LogicVRegister dst, in orr() argument
2055 int laneCount = LaneCountFromFormat(vform); in orr()
2057 result[i] = src.Uint(vform, i) | imm; in orr()
2059 dst.SetUintArray(vform, result); in orr()
2063 LogicVRegister Simulator::uxtl(VectorFormat vform, LogicVRegister dst, in uxtl() argument
2065 VectorFormat vform_half = VectorFormatHalfWidth(vform); in uxtl()
2067 dst.ClearForWrite(vform); in uxtl()
2068 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in uxtl()
2069 dst.SetUint(vform, i, src.Uint(vform_half, i)); in uxtl()
2074 LogicVRegister Simulator::sxtl(VectorFormat vform, LogicVRegister dst, in sxtl() argument
2076 VectorFormat vform_half = VectorFormatHalfWidth(vform); in sxtl()
2078 dst.ClearForWrite(vform); in sxtl()
2079 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in sxtl()
2080 dst.SetInt(vform, i, src.Int(vform_half, i)); in sxtl()
2085 LogicVRegister Simulator::uxtl2(VectorFormat vform, LogicVRegister dst, in uxtl2() argument
2087 VectorFormat vform_half = VectorFormatHalfWidth(vform); in uxtl2()
2088 int lane_count = LaneCountFromFormat(vform); in uxtl2()
2090 dst.ClearForWrite(vform); in uxtl2()
2092 dst.SetUint(vform, i, src.Uint(vform_half, lane_count + i)); in uxtl2()
2097 LogicVRegister Simulator::sxtl2(VectorFormat vform, LogicVRegister dst, in sxtl2() argument
2099 VectorFormat vform_half = VectorFormatHalfWidth(vform); in sxtl2()
2100 int lane_count = LaneCountFromFormat(vform); in sxtl2()
2102 dst.ClearForWrite(vform); in sxtl2()
2104 dst.SetInt(vform, i, src.Int(vform_half, lane_count + i)); in sxtl2()
2109 LogicVRegister Simulator::shrn(VectorFormat vform, LogicVRegister dst, in shrn() argument
2112 VectorFormat vform_src = VectorFormatDoubleWidth(vform); in shrn()
2113 VectorFormat vform_dst = vform; in shrn()
2118 LogicVRegister Simulator::shrn2(VectorFormat vform, LogicVRegister dst, in shrn2() argument
2121 VectorFormat vformsrc = VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)); in shrn2()
2122 VectorFormat vformdst = vform; in shrn2()
2127 LogicVRegister Simulator::rshrn(VectorFormat vform, LogicVRegister dst, in rshrn() argument
2130 VectorFormat vformsrc = VectorFormatDoubleWidth(vform); in rshrn()
2131 VectorFormat vformdst = vform; in rshrn()
2136 LogicVRegister Simulator::rshrn2(VectorFormat vform, LogicVRegister dst, in rshrn2() argument
2139 VectorFormat vformsrc = VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)); in rshrn2()
2140 VectorFormat vformdst = vform; in rshrn2()
2145 LogicVRegister Simulator::Table(VectorFormat vform, LogicVRegister dst, in Table() argument
2155 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in Table()
2158 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in Table()
2159 uint64_t j = ind.Uint(vform, i); in Table()
2166 dst.SetUintArray(vform, result); in Table()
2170 LogicVRegister Simulator::tbl(VectorFormat vform, LogicVRegister dst, in tbl() argument
2173 return Table(vform, dst, ind, true, &tab); in tbl()
2176 LogicVRegister Simulator::tbl(VectorFormat vform, LogicVRegister dst, in tbl() argument
2180 return Table(vform, dst, ind, true, &tab, &tab2); in tbl()
2183 LogicVRegister Simulator::tbl(VectorFormat vform, LogicVRegister dst, in tbl() argument
2188 return Table(vform, dst, ind, true, &tab, &tab2, &tab3); in tbl()
2191 LogicVRegister Simulator::tbl(VectorFormat vform, LogicVRegister dst, in tbl() argument
2197 return Table(vform, dst, ind, true, &tab, &tab2, &tab3, &tab4); in tbl()
2200 LogicVRegister Simulator::tbx(VectorFormat vform, LogicVRegister dst, in tbx() argument
2203 return Table(vform, dst, ind, false, &tab); in tbx()
2206 LogicVRegister Simulator::tbx(VectorFormat vform, LogicVRegister dst, in tbx() argument
2210 return Table(vform, dst, ind, false, &tab, &tab2); in tbx()
2213 LogicVRegister Simulator::tbx(VectorFormat vform, LogicVRegister dst, in tbx() argument
2218 return Table(vform, dst, ind, false, &tab, &tab2, &tab3); in tbx()
2221 LogicVRegister Simulator::tbx(VectorFormat vform, LogicVRegister dst, in tbx() argument
2227 return Table(vform, dst, ind, false, &tab, &tab2, &tab3, &tab4); in tbx()
2230 LogicVRegister Simulator::uqshrn(VectorFormat vform, LogicVRegister dst, in uqshrn() argument
2232 return shrn(vform, dst, src, shift).UnsignedSaturate(vform); in uqshrn()
2235 LogicVRegister Simulator::uqshrn2(VectorFormat vform, LogicVRegister dst, in uqshrn2() argument
2237 return shrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqshrn2()
2240 LogicVRegister Simulator::uqrshrn(VectorFormat vform, LogicVRegister dst, in uqrshrn() argument
2242 return rshrn(vform, dst, src, shift).UnsignedSaturate(vform); in uqrshrn()
2245 LogicVRegister Simulator::uqrshrn2(VectorFormat vform, LogicVRegister dst, in uqrshrn2() argument
2247 return rshrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqrshrn2()
2250 LogicVRegister Simulator::sqshrn(VectorFormat vform, LogicVRegister dst, in sqshrn() argument
2253 VectorFormat vformsrc = VectorFormatDoubleWidth(vform); in sqshrn()
2254 VectorFormat vformdst = vform; in sqshrn()
2259 LogicVRegister Simulator::sqshrn2(VectorFormat vform, LogicVRegister dst, in sqshrn2() argument
2262 VectorFormat vformsrc = VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)); in sqshrn2()
2263 VectorFormat vformdst = vform; in sqshrn2()
2268 LogicVRegister Simulator::sqrshrn(VectorFormat vform, LogicVRegister dst, in sqrshrn() argument
2271 VectorFormat vformsrc = VectorFormatDoubleWidth(vform); in sqrshrn()
2272 VectorFormat vformdst = vform; in sqrshrn()
2277 LogicVRegister Simulator::sqrshrn2(VectorFormat vform, LogicVRegister dst, in sqrshrn2() argument
2280 VectorFormat vformsrc = VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)); in sqrshrn2()
2281 VectorFormat vformdst = vform; in sqrshrn2()
2286 LogicVRegister Simulator::sqshrun(VectorFormat vform, LogicVRegister dst, in sqshrun() argument
2289 VectorFormat vformsrc = VectorFormatDoubleWidth(vform); in sqshrun()
2290 VectorFormat vformdst = vform; in sqshrun()
2295 LogicVRegister Simulator::sqshrun2(VectorFormat vform, LogicVRegister dst, in sqshrun2() argument
2298 VectorFormat vformsrc = VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)); in sqshrun2()
2299 VectorFormat vformdst = vform; in sqshrun2()
2304 LogicVRegister Simulator::sqrshrun(VectorFormat vform, LogicVRegister dst, in sqrshrun() argument
2307 VectorFormat vformsrc = VectorFormatDoubleWidth(vform); in sqrshrun()
2308 VectorFormat vformdst = vform; in sqrshrun()
2313 LogicVRegister Simulator::sqrshrun2(VectorFormat vform, LogicVRegister dst, in sqrshrun2() argument
2316 VectorFormat vformsrc = VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)); in sqrshrun2()
2317 VectorFormat vformdst = vform; in sqrshrun2()
2322 LogicVRegister Simulator::uaddl(VectorFormat vform, LogicVRegister dst, in uaddl() argument
2326 uxtl(vform, temp1, src1); in uaddl()
2327 uxtl(vform, temp2, src2); in uaddl()
2328 add(vform, dst, temp1, temp2); in uaddl()
2332 LogicVRegister Simulator::uaddl2(VectorFormat vform, LogicVRegister dst, in uaddl2() argument
2336 uxtl2(vform, temp1, src1); in uaddl2()
2337 uxtl2(vform, temp2, src2); in uaddl2()
2338 add(vform, dst, temp1, temp2); in uaddl2()
2342 LogicVRegister Simulator::uaddw(VectorFormat vform, LogicVRegister dst, in uaddw() argument
2346 uxtl(vform, temp, src2); in uaddw()
2347 add(vform, dst, src1, temp); in uaddw()
2351 LogicVRegister Simulator::uaddw2(VectorFormat vform, LogicVRegister dst, in uaddw2() argument
2355 uxtl2(vform, temp, src2); in uaddw2()
2356 add(vform, dst, src1, temp); in uaddw2()
2360 LogicVRegister Simulator::saddl(VectorFormat vform, LogicVRegister dst, in saddl() argument
2364 sxtl(vform, temp1, src1); in saddl()
2365 sxtl(vform, temp2, src2); in saddl()
2366 add(vform, dst, temp1, temp2); in saddl()
2370 LogicVRegister Simulator::saddl2(VectorFormat vform, LogicVRegister dst, in saddl2() argument
2374 sxtl2(vform, temp1, src1); in saddl2()
2375 sxtl2(vform, temp2, src2); in saddl2()
2376 add(vform, dst, temp1, temp2); in saddl2()
2380 LogicVRegister Simulator::saddw(VectorFormat vform, LogicVRegister dst, in saddw() argument
2384 sxtl(vform, temp, src2); in saddw()
2385 add(vform, dst, src1, temp); in saddw()
2389 LogicVRegister Simulator::saddw2(VectorFormat vform, LogicVRegister dst, in saddw2() argument
2393 sxtl2(vform, temp, src2); in saddw2()
2394 add(vform, dst, src1, temp); in saddw2()
2398 LogicVRegister Simulator::usubl(VectorFormat vform, LogicVRegister dst, in usubl() argument
2402 uxtl(vform, temp1, src1); in usubl()
2403 uxtl(vform, temp2, src2); in usubl()
2404 sub(vform, dst, temp1, temp2); in usubl()
2408 LogicVRegister Simulator::usubl2(VectorFormat vform, LogicVRegister dst, in usubl2() argument
2412 uxtl2(vform, temp1, src1); in usubl2()
2413 uxtl2(vform, temp2, src2); in usubl2()
2414 sub(vform, dst, temp1, temp2); in usubl2()
2418 LogicVRegister Simulator::usubw(VectorFormat vform, LogicVRegister dst, in usubw() argument
2422 uxtl(vform, temp, src2); in usubw()
2423 sub(vform, dst, src1, temp); in usubw()
2427 LogicVRegister Simulator::usubw2(VectorFormat vform, LogicVRegister dst, in usubw2() argument
2431 uxtl2(vform, temp, src2); in usubw2()
2432 sub(vform, dst, src1, temp); in usubw2()
2436 LogicVRegister Simulator::ssubl(VectorFormat vform, LogicVRegister dst, in ssubl() argument
2440 sxtl(vform, temp1, src1); in ssubl()
2441 sxtl(vform, temp2, src2); in ssubl()
2442 sub(vform, dst, temp1, temp2); in ssubl()
2446 LogicVRegister Simulator::ssubl2(VectorFormat vform, LogicVRegister dst, in ssubl2() argument
2450 sxtl2(vform, temp1, src1); in ssubl2()
2451 sxtl2(vform, temp2, src2); in ssubl2()
2452 sub(vform, dst, temp1, temp2); in ssubl2()
2456 LogicVRegister Simulator::ssubw(VectorFormat vform, LogicVRegister dst, in ssubw() argument
2460 sxtl(vform, temp, src2); in ssubw()
2461 sub(vform, dst, src1, temp); in ssubw()
2465 LogicVRegister Simulator::ssubw2(VectorFormat vform, LogicVRegister dst, in ssubw2() argument
2469 sxtl2(vform, temp, src2); in ssubw2()
2470 sub(vform, dst, src1, temp); in ssubw2()
2474 LogicVRegister Simulator::uabal(VectorFormat vform, LogicVRegister dst, in uabal() argument
2478 uxtl(vform, temp1, src1); in uabal()
2479 uxtl(vform, temp2, src2); in uabal()
2480 uaba(vform, dst, temp1, temp2); in uabal()
2484 LogicVRegister Simulator::uabal2(VectorFormat vform, LogicVRegister dst, in uabal2() argument
2488 uxtl2(vform, temp1, src1); in uabal2()
2489 uxtl2(vform, temp2, src2); in uabal2()
2490 uaba(vform, dst, temp1, temp2); in uabal2()
2494 LogicVRegister Simulator::sabal(VectorFormat vform, LogicVRegister dst, in sabal() argument
2498 sxtl(vform, temp1, src1); in sabal()
2499 sxtl(vform, temp2, src2); in sabal()
2500 saba(vform, dst, temp1, temp2); in sabal()
2504 LogicVRegister Simulator::sabal2(VectorFormat vform, LogicVRegister dst, in sabal2() argument
2508 sxtl2(vform, temp1, src1); in sabal2()
2509 sxtl2(vform, temp2, src2); in sabal2()
2510 saba(vform, dst, temp1, temp2); in sabal2()
2514 LogicVRegister Simulator::uabdl(VectorFormat vform, LogicVRegister dst, in uabdl() argument
2518 uxtl(vform, temp1, src1); in uabdl()
2519 uxtl(vform, temp2, src2); in uabdl()
2520 AbsDiff(vform, dst, temp1, temp2, false); in uabdl()
2524 LogicVRegister Simulator::uabdl2(VectorFormat vform, LogicVRegister dst, in uabdl2() argument
2528 uxtl2(vform, temp1, src1); in uabdl2()
2529 uxtl2(vform, temp2, src2); in uabdl2()
2530 AbsDiff(vform, dst, temp1, temp2, false); in uabdl2()
2534 LogicVRegister Simulator::sabdl(VectorFormat vform, LogicVRegister dst, in sabdl() argument
2538 sxtl(vform, temp1, src1); in sabdl()
2539 sxtl(vform, temp2, src2); in sabdl()
2540 AbsDiff(vform, dst, temp1, temp2, true); in sabdl()
2544 LogicVRegister Simulator::sabdl2(VectorFormat vform, LogicVRegister dst, in sabdl2() argument
2548 sxtl2(vform, temp1, src1); in sabdl2()
2549 sxtl2(vform, temp2, src2); in sabdl2()
2550 AbsDiff(vform, dst, temp1, temp2, true); in sabdl2()
2554 LogicVRegister Simulator::umull(VectorFormat vform, LogicVRegister dst, in umull() argument
2558 uxtl(vform, temp1, src1); in umull()
2559 uxtl(vform, temp2, src2); in umull()
2560 mul(vform, dst, temp1, temp2); in umull()
2564 LogicVRegister Simulator::umull2(VectorFormat vform, LogicVRegister dst, in umull2() argument
2568 uxtl2(vform, temp1, src1); in umull2()
2569 uxtl2(vform, temp2, src2); in umull2()
2570 mul(vform, dst, temp1, temp2); in umull2()
2574 LogicVRegister Simulator::smull(VectorFormat vform, LogicVRegister dst, in smull() argument
2578 sxtl(vform, temp1, src1); in smull()
2579 sxtl(vform, temp2, src2); in smull()
2580 mul(vform, dst, temp1, temp2); in smull()
2584 LogicVRegister Simulator::smull2(VectorFormat vform, LogicVRegister dst, in smull2() argument
2588 sxtl2(vform, temp1, src1); in smull2()
2589 sxtl2(vform, temp2, src2); in smull2()
2590 mul(vform, dst, temp1, temp2); in smull2()
2594 LogicVRegister Simulator::umlsl(VectorFormat vform, LogicVRegister dst, in umlsl() argument
2598 uxtl(vform, temp1, src1); in umlsl()
2599 uxtl(vform, temp2, src2); in umlsl()
2600 mls(vform, dst, temp1, temp2); in umlsl()
2604 LogicVRegister Simulator::umlsl2(VectorFormat vform, LogicVRegister dst, in umlsl2() argument
2608 uxtl2(vform, temp1, src1); in umlsl2()
2609 uxtl2(vform, temp2, src2); in umlsl2()
2610 mls(vform, dst, temp1, temp2); in umlsl2()
2614 LogicVRegister Simulator::smlsl(VectorFormat vform, LogicVRegister dst, in smlsl() argument
2618 sxtl(vform, temp1, src1); in smlsl()
2619 sxtl(vform, temp2, src2); in smlsl()
2620 mls(vform, dst, temp1, temp2); in smlsl()
2624 LogicVRegister Simulator::smlsl2(VectorFormat vform, LogicVRegister dst, in smlsl2() argument
2628 sxtl2(vform, temp1, src1); in smlsl2()
2629 sxtl2(vform, temp2, src2); in smlsl2()
2630 mls(vform, dst, temp1, temp2); in smlsl2()
2634 LogicVRegister Simulator::umlal(VectorFormat vform, LogicVRegister dst, in umlal() argument
2638 uxtl(vform, temp1, src1); in umlal()
2639 uxtl(vform, temp2, src2); in umlal()
2640 mla(vform, dst, temp1, temp2); in umlal()
2644 LogicVRegister Simulator::umlal2(VectorFormat vform, LogicVRegister dst, in umlal2() argument
2648 uxtl2(vform, temp1, src1); in umlal2()
2649 uxtl2(vform, temp2, src2); in umlal2()
2650 mla(vform, dst, temp1, temp2); in umlal2()
2654 LogicVRegister Simulator::smlal(VectorFormat vform, LogicVRegister dst, in smlal() argument
2658 sxtl(vform, temp1, src1); in smlal()
2659 sxtl(vform, temp2, src2); in smlal()
2660 mla(vform, dst, temp1, temp2); in smlal()
2664 LogicVRegister Simulator::smlal2(VectorFormat vform, LogicVRegister dst, in smlal2() argument
2668 sxtl2(vform, temp1, src1); in smlal2()
2669 sxtl2(vform, temp2, src2); in smlal2()
2670 mla(vform, dst, temp1, temp2); in smlal2()
2674 LogicVRegister Simulator::sqdmlal(VectorFormat vform, LogicVRegister dst, in sqdmlal() argument
2678 LogicVRegister product = sqdmull(vform, temp, src1, src2); in sqdmlal()
2679 return add(vform, dst, dst, product).SignedSaturate(vform); in sqdmlal()
2682 LogicVRegister Simulator::sqdmlal2(VectorFormat vform, LogicVRegister dst, in sqdmlal2() argument
2686 LogicVRegister product = sqdmull2(vform, temp, src1, src2); in sqdmlal2()
2687 return add(vform, dst, dst, product).SignedSaturate(vform); in sqdmlal2()
2690 LogicVRegister Simulator::sqdmlsl(VectorFormat vform, LogicVRegister dst, in sqdmlsl() argument
2694 LogicVRegister product = sqdmull(vform, temp, src1, src2); in sqdmlsl()
2695 return sub(vform, dst, dst, product).SignedSaturate(vform); in sqdmlsl()
2698 LogicVRegister Simulator::sqdmlsl2(VectorFormat vform, LogicVRegister dst, in sqdmlsl2() argument
2702 LogicVRegister product = sqdmull2(vform, temp, src1, src2); in sqdmlsl2()
2703 return sub(vform, dst, dst, product).SignedSaturate(vform); in sqdmlsl2()
2706 LogicVRegister Simulator::sqdmull(VectorFormat vform, LogicVRegister dst, in sqdmull() argument
2710 LogicVRegister product = smull(vform, temp, src1, src2); in sqdmull()
2711 return add(vform, dst, product, product).SignedSaturate(vform); in sqdmull()
2714 LogicVRegister Simulator::sqdmull2(VectorFormat vform, LogicVRegister dst, in sqdmull2() argument
2718 LogicVRegister product = smull2(vform, temp, src1, src2); in sqdmull2()
2719 return add(vform, dst, product, product).SignedSaturate(vform); in sqdmull2()
2722 LogicVRegister Simulator::sqrdmulh(VectorFormat vform, LogicVRegister dst, in sqrdmulh() argument
2729 int esize = LaneSizeInBitsFromFormat(vform); in sqrdmulh()
2733 dst.ClearForWrite(vform); in sqrdmulh()
2734 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in sqrdmulh()
2735 product = src1.Int(vform, i) * src2.Int(vform, i); in sqrdmulh()
2739 if (product > MaxIntFromFormat(vform)) { in sqrdmulh()
2740 product = MaxIntFromFormat(vform); in sqrdmulh()
2741 } else if (product < MinIntFromFormat(vform)) { in sqrdmulh()
2742 product = MinIntFromFormat(vform); in sqrdmulh()
2744 dst.SetInt(vform, i, product); in sqrdmulh()
2749 LogicVRegister Simulator::sqdmulh(VectorFormat vform, LogicVRegister dst, in sqdmulh() argument
2752 return sqrdmulh(vform, dst, src1, src2, false); in sqdmulh()
2755 LogicVRegister Simulator::addhn(VectorFormat vform, LogicVRegister dst, in addhn() argument
2759 add(VectorFormatDoubleWidth(vform), temp, src1, src2); in addhn()
2760 shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in addhn()
2764 LogicVRegister Simulator::addhn2(VectorFormat vform, LogicVRegister dst, in addhn2() argument
2768 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2); in addhn2()
2769 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in addhn2()
2773 LogicVRegister Simulator::raddhn(VectorFormat vform, LogicVRegister dst, in raddhn() argument
2777 add(VectorFormatDoubleWidth(vform), temp, src1, src2); in raddhn()
2778 rshrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in raddhn()
2782 LogicVRegister Simulator::raddhn2(VectorFormat vform, LogicVRegister dst, in raddhn2() argument
2786 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2); in raddhn2()
2787 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in raddhn2()
2791 LogicVRegister Simulator::subhn(VectorFormat vform, LogicVRegister dst, in subhn() argument
2795 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); in subhn()
2796 shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in subhn()
2800 LogicVRegister Simulator::subhn2(VectorFormat vform, LogicVRegister dst, in subhn2() argument
2804 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2); in subhn2()
2805 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in subhn2()
2809 LogicVRegister Simulator::rsubhn(VectorFormat vform, LogicVRegister dst, in rsubhn() argument
2813 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); in rsubhn()
2814 rshrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in rsubhn()
2818 LogicVRegister Simulator::rsubhn2(VectorFormat vform, LogicVRegister dst, in rsubhn2() argument
2822 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2); in rsubhn2()
2823 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in rsubhn2()
2827 LogicVRegister Simulator::trn1(VectorFormat vform, LogicVRegister dst, in trn1() argument
2831 int laneCount = LaneCountFromFormat(vform); in trn1()
2834 result[2 * i] = src1.Uint(vform, 2 * i); in trn1()
2835 result[(2 * i) + 1] = src2.Uint(vform, 2 * i); in trn1()
2838 dst.SetUintArray(vform, result); in trn1()
2842 LogicVRegister Simulator::trn2(VectorFormat vform, LogicVRegister dst, in trn2() argument
2846 int laneCount = LaneCountFromFormat(vform); in trn2()
2849 result[2 * i] = src1.Uint(vform, (2 * i) + 1); in trn2()
2850 result[(2 * i) + 1] = src2.Uint(vform, (2 * i) + 1); in trn2()
2853 dst.SetUintArray(vform, result); in trn2()
2857 LogicVRegister Simulator::zip1(VectorFormat vform, LogicVRegister dst, in zip1() argument
2861 int laneCount = LaneCountFromFormat(vform); in zip1()
2864 result[2 * i] = src1.Uint(vform, i); in zip1()
2865 result[(2 * i) + 1] = src2.Uint(vform, i); in zip1()
2868 dst.SetUintArray(vform, result); in zip1()
2872 LogicVRegister Simulator::zip2(VectorFormat vform, LogicVRegister dst, in zip2() argument
2876 int laneCount = LaneCountFromFormat(vform); in zip2()
2879 result[2 * i] = src1.Uint(vform, pairs + i); in zip2()
2880 result[(2 * i) + 1] = src2.Uint(vform, pairs + i); in zip2()
2883 dst.SetUintArray(vform, result); in zip2()
2887 LogicVRegister Simulator::uzp1(VectorFormat vform, LogicVRegister dst, in uzp1() argument
2891 int laneCount = LaneCountFromFormat(vform); in uzp1()
2893 result[i] = src1.Uint(vform, i); in uzp1()
2894 result[laneCount + i] = src2.Uint(vform, i); in uzp1()
2897 dst.ClearForWrite(vform); in uzp1()
2899 dst.SetUint(vform, i, result[2 * i]); in uzp1()
2904 LogicVRegister Simulator::uzp2(VectorFormat vform, LogicVRegister dst, in uzp2() argument
2908 int laneCount = LaneCountFromFormat(vform); in uzp2()
2910 result[i] = src1.Uint(vform, i); in uzp2()
2911 result[laneCount + i] = src2.Uint(vform, i); in uzp2()
2914 dst.ClearForWrite(vform); in uzp2()
2916 dst.SetUint(vform, i, result[(2 * i) + 1]); in uzp2()
3261 LogicVRegister Simulator::FN(VectorFormat vform, LogicVRegister dst, \
3264 dst.ClearForWrite(vform); \
3265 for (int i = 0; i < LaneCountFromFormat(vform); i++) { \
3282 LogicVRegister Simulator::FN(VectorFormat vform, LogicVRegister dst, \
3285 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { \
3286 FN<float>(vform, dst, src1, src2); \
3288 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); \
3289 FN<double>(vform, dst, src1, src2); \
3296 LogicVRegister Simulator::fnmul(VectorFormat vform, LogicVRegister dst, in NEON_FP3SAME_LIST()
3300 LogicVRegister product = fmul(vform, temp, src1, src2); in NEON_FP3SAME_LIST()
3301 return fneg(vform, dst, product); in NEON_FP3SAME_LIST()
3305 LogicVRegister Simulator::frecps(VectorFormat vform, LogicVRegister dst, in frecps() argument
3308 dst.ClearForWrite(vform); in frecps()
3309 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in frecps()
3318 LogicVRegister Simulator::frecps(VectorFormat vform, LogicVRegister dst, in frecps() argument
3321 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in frecps()
3322 frecps<float>(vform, dst, src1, src2); in frecps()
3324 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in frecps()
3325 frecps<double>(vform, dst, src1, src2); in frecps()
3331 LogicVRegister Simulator::frsqrts(VectorFormat vform, LogicVRegister dst, in frsqrts() argument
3334 dst.ClearForWrite(vform); in frsqrts()
3335 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in frsqrts()
3344 LogicVRegister Simulator::frsqrts(VectorFormat vform, LogicVRegister dst, in frsqrts() argument
3347 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in frsqrts()
3348 frsqrts<float>(vform, dst, src1, src2); in frsqrts()
3350 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in frsqrts()
3351 frsqrts<double>(vform, dst, src1, src2); in frsqrts()
3357 LogicVRegister Simulator::fcmp(VectorFormat vform, LogicVRegister dst, in fcmp() argument
3360 dst.ClearForWrite(vform); in fcmp()
3361 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fcmp()
3387 dst.SetUint(vform, i, result ? MaxUintFromFormat(vform) : 0); in fcmp()
3392 LogicVRegister Simulator::fcmp(VectorFormat vform, LogicVRegister dst, in fcmp() argument
3395 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fcmp()
3396 fcmp<float>(vform, dst, src1, src2, cond); in fcmp()
3398 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fcmp()
3399 fcmp<double>(vform, dst, src1, src2, cond); in fcmp()
3404 LogicVRegister Simulator::fcmp_zero(VectorFormat vform, LogicVRegister dst, in fcmp_zero() argument
3407 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fcmp_zero()
3409 dup_immediate(vform, temp, bit_cast<uint32_t>(0.0f)); in fcmp_zero()
3410 fcmp<float>(vform, dst, src, zero_reg, cond); in fcmp_zero()
3412 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fcmp_zero()
3414 dup_immediate(vform, temp, bit_cast<uint64_t>(0.0)); in fcmp_zero()
3415 fcmp<double>(vform, dst, src, zero_reg, cond); in fcmp_zero()
3420 LogicVRegister Simulator::fabscmp(VectorFormat vform, LogicVRegister dst, in fabscmp() argument
3424 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fabscmp()
3425 LogicVRegister abs_src1 = fabs_<float>(vform, temp1, src1); in fabscmp()
3426 LogicVRegister abs_src2 = fabs_<float>(vform, temp2, src2); in fabscmp()
3427 fcmp<float>(vform, dst, abs_src1, abs_src2, cond); in fabscmp()
3429 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fabscmp()
3430 LogicVRegister abs_src1 = fabs_<double>(vform, temp1, src1); in fabscmp()
3431 LogicVRegister abs_src2 = fabs_<double>(vform, temp2, src2); in fabscmp()
3432 fcmp<double>(vform, dst, abs_src1, abs_src2, cond); in fabscmp()
3438 LogicVRegister Simulator::fmla(VectorFormat vform, LogicVRegister dst, in fmla() argument
3441 dst.ClearForWrite(vform); in fmla()
3442 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fmla()
3452 LogicVRegister Simulator::fmla(VectorFormat vform, LogicVRegister dst, in fmla() argument
3455 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fmla()
3456 fmla<float>(vform, dst, src1, src2); in fmla()
3458 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fmla()
3459 fmla<double>(vform, dst, src1, src2); in fmla()
3465 LogicVRegister Simulator::fmls(VectorFormat vform, LogicVRegister dst, in fmls() argument
3468 dst.ClearForWrite(vform); in fmls()
3469 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fmls()
3479 LogicVRegister Simulator::fmls(VectorFormat vform, LogicVRegister dst, in fmls() argument
3482 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fmls()
3483 fmls<float>(vform, dst, src1, src2); in fmls()
3485 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fmls()
3486 fmls<double>(vform, dst, src1, src2); in fmls()
3492 LogicVRegister Simulator::fneg(VectorFormat vform, LogicVRegister dst, in fneg() argument
3494 dst.ClearForWrite(vform); in fneg()
3495 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fneg()
3503 LogicVRegister Simulator::fneg(VectorFormat vform, LogicVRegister dst, in fneg() argument
3505 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fneg()
3506 fneg<float>(vform, dst, src); in fneg()
3508 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fneg()
3509 fneg<double>(vform, dst, src); in fneg()
3515 LogicVRegister Simulator::fabs_(VectorFormat vform, LogicVRegister dst, in fabs_() argument
3517 dst.ClearForWrite(vform); in fabs_()
3518 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fabs_()
3528 LogicVRegister Simulator::fabs_(VectorFormat vform, LogicVRegister dst, in fabs_() argument
3530 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fabs_()
3531 fabs_<float>(vform, dst, src); in fabs_()
3533 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fabs_()
3534 fabs_<double>(vform, dst, src); in fabs_()
3539 LogicVRegister Simulator::fabd(VectorFormat vform, LogicVRegister dst, in fabd() argument
3543 fsub(vform, temp, src1, src2); in fabd()
3544 fabs_(vform, dst, temp); in fabd()
3548 LogicVRegister Simulator::fsqrt(VectorFormat vform, LogicVRegister dst, in fsqrt() argument
3550 dst.ClearForWrite(vform); in fsqrt()
3551 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fsqrt()
3552 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fsqrt()
3557 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fsqrt()
3558 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fsqrt()
3567 LogicVRegister Simulator::FNP(VectorFormat vform, LogicVRegister dst, \
3571 uzp1(vform, temp1, src1, src2); \
3572 uzp2(vform, temp2, src1, src2); \
3573 FN(vform, dst, temp1, temp2); \
3577 LogicVRegister Simulator::FNP(VectorFormat vform, LogicVRegister dst, \
3579 if (vform == kFormatS) { \
3583 DCHECK_EQ(vform, kFormatD); \
3587 dst.ClearForWrite(vform); \
3593 LogicVRegister Simulator::FMinMaxV(VectorFormat vform, LogicVRegister dst, in NEON_FPPAIRWISE_LIST()
3595 DCHECK_EQ(vform, kFormat4S); in NEON_FPPAIRWISE_LIST()
3596 USE(vform); in NEON_FPPAIRWISE_LIST()
3605 LogicVRegister Simulator::fmaxv(VectorFormat vform, LogicVRegister dst, in fmaxv() argument
3607 return FMinMaxV(vform, dst, src, &Simulator::FPMax); in fmaxv()
3610 LogicVRegister Simulator::fminv(VectorFormat vform, LogicVRegister dst, in fminv() argument
3612 return FMinMaxV(vform, dst, src, &Simulator::FPMin); in fminv()
3615 LogicVRegister Simulator::fmaxnmv(VectorFormat vform, LogicVRegister dst, in fmaxnmv() argument
3617 return FMinMaxV(vform, dst, src, &Simulator::FPMaxNM); in fmaxnmv()
3620 LogicVRegister Simulator::fminnmv(VectorFormat vform, LogicVRegister dst, in fminnmv() argument
3622 return FMinMaxV(vform, dst, src, &Simulator::FPMinNM); in fminnmv()
3625 LogicVRegister Simulator::fmul(VectorFormat vform, LogicVRegister dst, in fmul() argument
3628 dst.ClearForWrite(vform); in fmul()
3630 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fmul()
3632 fmul<float>(vform, dst, src1, index_reg); in fmul()
3634 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fmul()
3636 fmul<double>(vform, dst, src1, index_reg); in fmul()
3641 LogicVRegister Simulator::fmla(VectorFormat vform, LogicVRegister dst, in fmla() argument
3644 dst.ClearForWrite(vform); in fmla()
3646 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fmla()
3648 fmla<float>(vform, dst, src1, index_reg); in fmla()
3650 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fmla()
3652 fmla<double>(vform, dst, src1, index_reg); in fmla()
3657 LogicVRegister Simulator::fmls(VectorFormat vform, LogicVRegister dst, in fmls() argument
3660 dst.ClearForWrite(vform); in fmls()
3662 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fmls()
3664 fmls<float>(vform, dst, src1, index_reg); in fmls()
3666 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fmls()
3668 fmls<double>(vform, dst, src1, index_reg); in fmls()
3673 LogicVRegister Simulator::fmulx(VectorFormat vform, LogicVRegister dst, in fmulx() argument
3676 dst.ClearForWrite(vform); in fmulx()
3678 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fmulx()
3680 fmulx<float>(vform, dst, src1, index_reg); in fmulx()
3683 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fmulx()
3685 fmulx<double>(vform, dst, src1, index_reg); in fmulx()
3690 LogicVRegister Simulator::frint(VectorFormat vform, LogicVRegister dst, in frint() argument
3694 dst.ClearForWrite(vform); in frint()
3695 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in frint()
3696 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in frint()
3705 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in frint()
3706 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in frint()
3718 LogicVRegister Simulator::fcvts(VectorFormat vform, LogicVRegister dst, in fcvts() argument
3721 dst.ClearForWrite(vform); in fcvts()
3722 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fcvts()
3723 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fcvts()
3725 dst.SetInt(vform, i, FPToInt32(op, rounding_mode)); in fcvts()
3728 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fcvts()
3729 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fcvts()
3731 dst.SetInt(vform, i, FPToInt64(op, rounding_mode)); in fcvts()
3737 LogicVRegister Simulator::fcvtu(VectorFormat vform, LogicVRegister dst, in fcvtu() argument
3740 dst.ClearForWrite(vform); in fcvtu()
3741 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fcvtu()
3742 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fcvtu()
3744 dst.SetUint(vform, i, FPToUInt32(op, rounding_mode)); in fcvtu()
3747 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fcvtu()
3748 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fcvtu()
3750 dst.SetUint(vform, i, FPToUInt64(op, rounding_mode)); in fcvtu()
3756 LogicVRegister Simulator::fcvtl(VectorFormat vform, LogicVRegister dst, in fcvtl() argument
3758 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fcvtl()
3759 for (int i = LaneCountFromFormat(vform) - 1; i >= 0; i--) { in fcvtl()
3763 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fcvtl()
3764 for (int i = LaneCountFromFormat(vform) - 1; i >= 0; i--) { in fcvtl()
3771 LogicVRegister Simulator::fcvtl2(VectorFormat vform, LogicVRegister dst, in fcvtl2() argument
3773 int lane_count = LaneCountFromFormat(vform); in fcvtl2()
3774 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fcvtl2()
3779 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in fcvtl2()
3787 LogicVRegister Simulator::fcvtn(VectorFormat vform, LogicVRegister dst, in fcvtn() argument
3789 if (LaneSizeInBytesFromFormat(vform) == kHRegSize) { in fcvtn()
3790 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fcvtn()
3794 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kSRegSize); in fcvtn()
3795 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fcvtn()
3802 LogicVRegister Simulator::fcvtn2(VectorFormat vform, LogicVRegister dst, in fcvtn2() argument
3804 int lane_count = LaneCountFromFormat(vform) / 2; in fcvtn2()
3805 if (LaneSizeInBytesFromFormat(vform) == kHRegSize) { in fcvtn2()
3810 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kSRegSize); in fcvtn2()
3818 LogicVRegister Simulator::fcvtxn(VectorFormat vform, LogicVRegister dst, in fcvtxn() argument
3820 dst.ClearForWrite(vform); in fcvtxn()
3821 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kSRegSize); in fcvtxn()
3822 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in fcvtxn()
3828 LogicVRegister Simulator::fcvtxn2(VectorFormat vform, LogicVRegister dst, in fcvtxn2() argument
3830 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kSRegSize); in fcvtxn2()
3831 int lane_count = LaneCountFromFormat(vform) / 2; in fcvtxn2()
3925 LogicVRegister Simulator::frsqrte(VectorFormat vform, LogicVRegister dst, in frsqrte() argument
3927 dst.ClearForWrite(vform); in frsqrte()
3928 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in frsqrte()
3929 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in frsqrte()
3934 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in frsqrte()
3935 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in frsqrte()
4046 LogicVRegister Simulator::frecpe(VectorFormat vform, LogicVRegister dst, in frecpe() argument
4048 dst.ClearForWrite(vform); in frecpe()
4049 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in frecpe()
4050 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in frecpe()
4055 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in frecpe()
4056 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in frecpe()
4064 LogicVRegister Simulator::ursqrte(VectorFormat vform, LogicVRegister dst, in ursqrte() argument
4066 dst.ClearForWrite(vform); in ursqrte()
4070 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ursqrte()
4071 operand = src.Uint(vform, i); in ursqrte()
4079 dst.SetUint(vform, i, result); in ursqrte()
4094 LogicVRegister Simulator::urecpe(VectorFormat vform, LogicVRegister dst, in urecpe() argument
4096 dst.ClearForWrite(vform); in urecpe()
4100 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in urecpe()
4101 operand = src.Uint(vform, i); in urecpe()
4109 dst.SetUint(vform, i, result); in urecpe()
4115 LogicVRegister Simulator::frecpx(VectorFormat vform, LogicVRegister dst, in frecpx() argument
4117 dst.ClearForWrite(vform); in frecpx()
4118 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in frecpx()
4143 LogicVRegister Simulator::frecpx(VectorFormat vform, LogicVRegister dst, in frecpx() argument
4145 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in frecpx()
4146 frecpx<float>(vform, dst, src); in frecpx()
4148 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in frecpx()
4149 frecpx<double>(vform, dst, src); in frecpx()
4154 LogicVRegister Simulator::scvtf(VectorFormat vform, LogicVRegister dst, in scvtf() argument
4157 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in scvtf()
4158 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in scvtf()
4162 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in scvtf()
4170 LogicVRegister Simulator::ucvtf(VectorFormat vform, LogicVRegister dst, in ucvtf() argument
4173 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ucvtf()
4174 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in ucvtf()
4178 DCHECK_EQ(LaneSizeInBytesFromFormat(vform), kDRegSize); in ucvtf()