115         return Operand(InputRegister32(index), LSL, InputInt5(index + 1));  in InputOperand2_32()
117         return Operand(InputRegister32(index), LSR, InputInt5(index + 1));  in InputOperand2_32()
119         return Operand(InputRegister32(index), ASR, InputInt5(index + 1));  in InputOperand2_32()
121         return Operand(InputRegister32(index), ROR, InputInt5(index + 1));  in InputOperand2_32()
1182       __ Sbfx(i.OutputRegister32(), i.InputRegister32(0), i.InputInt5(1),  in AssembleArchInstruction()
1183               i.InputInt5(2));  in AssembleArchInstruction()
1190       __ Ubfx(i.OutputRegister32(), i.InputRegister32(0), i.InputInt5(1),  in AssembleArchInstruction()
1194       __ Ubfiz(i.OutputRegister32(), i.InputRegister32(0), i.InputInt5(1),  in AssembleArchInstruction()
1195                i.InputInt5(2));  in AssembleArchInstruction()
1790              i.InputInt5(1));  in AssembleArchInstruction()
1795               i.InputInt5(1));  in AssembleArchInstruction()
1819               i.InputInt5(1));  in AssembleArchInstruction()
1849              i.InputInt5(1));  in AssembleArchInstruction()
1854               i.InputInt5(1));  in AssembleArchInstruction()
1900               i.InputInt5(1));  in AssembleArchInstruction()
1944              i.InputInt5(1));  in AssembleArchInstruction()
1949               i.InputSimd128Register(0).V16B(), i.InputInt5(1));  in AssembleArchInstruction()
1985               i.InputSimd128Register(0).V16B(), i.InputInt5(1));  in AssembleArchInstruction()
2190         __ Tbz(i.InputRegister32(0), i.InputInt5(1), tlabel);  in AssembleArchBranch()
2193         __ Tbnz(i.InputRegister32(0), i.InputInt5(1), tlabel);  in AssembleArchBranch()