code-generator-mips64.cc - OpenGrok cross reference for /external/v8/src/compiler/mips64/code-generator-mips64.cc

Lines Matching refs:InputOperand
97   Operand InputOperand(size_t index) {  in InputOperand()  function in v8::internal::compiler::MipsOperandConverter
959       __ Addu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
962       __ Daddu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
965       __ DaddOverflow(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1),  in AssembleArchInstruction()
969       __ Subu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
972       __ Dsubu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
975       __ DsubOverflow(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1),  in AssembleArchInstruction()
979       __ Mul(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
982       __ MulOverflow(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1),  in AssembleArchInstruction()
986       __ Mulh(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
989       __ Mulhu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
992       __ Dmulh(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
995       __ Div(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1003       __ Divu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1011       __ Mod(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1014       __ Modu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1017       __ Dmul(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1020       __ Ddiv(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1028       __ Ddivu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1036       __ Dmod(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1039       __ Dmodu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1052       __ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1058         __ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1061         __ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1065       __ Or(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1071         __ Or(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1074         __ Or(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1079         __ Nor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1081         DCHECK_EQ(0, i.InputOperand(1).immediate());  in AssembleArchInstruction()
1089         __ Nor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1091         DCHECK_EQ(0, i.InputOperand(1).immediate());  in AssembleArchInstruction()
1097       __ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1103         __ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1106         __ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1139         int64_t imm = i.InputOperand(1).immediate();  in AssembleArchInstruction()
1149         int64_t imm = i.InputOperand(1).immediate();  in AssembleArchInstruction()
1160         int64_t imm = i.InputOperand(1).immediate();  in AssembleArchInstruction()
1195         int64_t imm = i.InputOperand(1).immediate();  in AssembleArchInstruction()
1209         int64_t imm = i.InputOperand(1).immediate();  in AssembleArchInstruction()
1223         int64_t imm = i.InputOperand(1).immediate();  in AssembleArchInstruction()
1232       __ Ror(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1235       __ Dror(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1238       __ And(kScratchReg, i.InputRegister(0), i.InputOperand(1));  in AssembleArchInstruction()
1250         __ li(i.OutputRegister(), i.InputOperand(0));  in AssembleArchInstruction()
1911       __ Assert(eq, static_cast<AbortReason>(i.InputOperand(2).immediate()),  in AssembleArchInstruction()
3049     __ Branch(tlabel, cc, i.InputRegister(0), i.InputOperand(1));  in AssembleBranchToLabels()
3091                              i.InputOperand(1),  in AssembleBranchPoisoning()
3285         Operand right = i.InputOperand(1);  in AssembleArchBoolean()
3327         Operand right = i.InputOperand(1);  in AssembleArchBoolean()
3336         Operand right = i.InputOperand(0);  in AssembleArchBoolean()
3345         Operand right = i.InputOperand(1);  in AssembleArchBoolean()
3354         Operand right = i.InputOperand(0);  in AssembleArchBoolean()