Lines Matching refs:InputOperand
36 Operand InputOperand(size_t index, int extra = 0) { in InputOperand() function in v8::internal::compiler::X64OperandConverter
377 __ asm_instr(i.InputOperand(0), i.InputImmediate(1)); \
383 __ asm_instr(i.InputRegister(0), i.InputOperand(1)); \
404 __ asm_instr(i.InputOperand(0), i.InputImmediate(1)); \
410 __ asm_instr(i.InputRegister(0), i.InputOperand(1)); \
423 __ asm_instr(i.OutputRegister(), i.InputOperand(0), \
430 __ asm_instr(i.OutputRegister(), i.InputOperand(1)); \
461 __ asm_instr(i.OutputRegister(), i.InputOperand(0)); \
470 __ asm_instr(i.InputDoubleRegister(0), i.InputOperand(1)); \
479 __ asm_instr(i.OutputDoubleRegister(), i.InputOperand(0)); \
491 i.InputOperand(1)); \
1100 __ imull(i.InputOperand(1)); in AssembleArchInstruction()
1107 __ mull(i.InputOperand(1)); in AssembleArchInstruction()
1178 __ Lzcntq(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1185 __ Lzcntl(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1192 __ Tzcntq(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1199 __ Tzcntl(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1206 __ Popcntq(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1213 __ Popcntl(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1271 __ Cvttss2si(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1278 __ Cvttss2siq(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1345 __ Ucomiss(i.InputDoubleRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
1359 __ Movss(i.InputDoubleRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
1370 __ Ucomiss(i.InputDoubleRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
1380 __ Movss(kScratchDoubleReg, i.InputOperand(1)); in AssembleArchInstruction()
1389 __ Movss(i.InputDoubleRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
1400 __ Ucomisd(i.InputDoubleRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
1414 __ Movsd(i.InputDoubleRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
1425 __ Ucomisd(i.InputDoubleRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
1435 __ Movsd(kScratchDoubleReg, i.InputOperand(1)); in AssembleArchInstruction()
1444 __ Movsd(i.InputDoubleRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
1481 __ Cvttsd2si(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1488 __ Cvttsd2siq(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1499 __ Cvttss2siq(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1509 __ Ucomiss(kScratchDoubleReg, i.InputOperand(0)); in AssembleArchInstruction()
1528 __ Cvttsd2siq(i.OutputRegister(0), i.InputOperand(0)); in AssembleArchInstruction()
1538 __ Ucomisd(kScratchDoubleReg, i.InputOperand(0)); in AssembleArchInstruction()
1559 __ Cvttss2uiq(i.OutputRegister(), i.InputOperand(0), &fail); in AssembleArchInstruction()
1571 __ Cvttsd2uiq(i.OutputRegister(), i.InputOperand(0), &fail); in AssembleArchInstruction()
1581 __ Cvtlsi2sd(i.OutputDoubleRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1588 __ Cvtlsi2ss(i.OutputDoubleRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1595 __ Cvtqsi2ss(i.OutputDoubleRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1602 __ Cvtqsi2sd(i.OutputDoubleRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1609 __ Cvtqui2ss(i.OutputDoubleRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1616 __ Cvtqui2sd(i.OutputDoubleRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1623 __ Cvtlui2sd(i.OutputDoubleRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1630 __ Cvtlui2ss(i.OutputDoubleRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1635 __ movl(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1642 __ movl(i.OutputRegister(), i.InputOperand(0, kDoubleSize / 2)); in AssembleArchInstruction()
1651 __ Pinsrd(i.OutputDoubleRegister(), i.InputOperand(1), 0); in AssembleArchInstruction()
1658 __ Pinsrd(i.OutputDoubleRegister(), i.InputOperand(1), 1); in AssembleArchInstruction()
1665 __ Movd(i.OutputDoubleRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1673 __ vucomiss(i.InputDoubleRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
1697 __ vucomisd(i.InputDoubleRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
1726 i.InputOperand(0)); in AssembleArchInstruction()
1740 i.InputOperand(0)); in AssembleArchInstruction()
1754 i.InputOperand(0)); in AssembleArchInstruction()
1768 i.InputOperand(0)); in AssembleArchInstruction()
1852 __ movl(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1935 __ movl(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1942 __ movq(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1951 __ movss(i.OutputDoubleRegister(), i.InputOperand(0)); in AssembleArchInstruction()
1958 __ Movsd(i.OutputDoubleRegister(), i.InputOperand(0)); in AssembleArchInstruction()
2077 __ pushq(i.InputOperand(0)); in AssembleArchInstruction()
2083 __ Movups(kScratchDoubleReg, i.InputOperand(0)); in AssembleArchInstruction()
2124 __ movss(dst, i.InputOperand(0)); in AssembleArchInstruction()
2247 __ Pinsrd(i.OutputSimd128Register(), i.InputOperand(2), i.InputInt8(1)); in AssembleArchInstruction()
2379 __ pinsrw(i.OutputSimd128Register(), i.InputOperand(2), i.InputInt8(1)); in AssembleArchInstruction()
2523 __ pinsrb(i.OutputSimd128Register(), i.InputOperand(2), i.InputInt8(1)); in AssembleArchInstruction()