84   supported_ |= 1u << MIPS_SIMD;  in ProbeImpl()
100   supported_ |= 1u << MIPS_SIMD;  in ProbeImpl()
102   if (cpu.has_msa()) supported_ |= 1u << MIPS_SIMD;  in ProbeImpl()
1339   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in GenInstrMsaI8()
1348   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in GenInstrMsaI5()
1362   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in GenInstrMsaBit()
1371   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in GenInstrMsaI10()
1381   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in GenInstrMsa3R()
1391   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in GenInstrMsaElm()
1401   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in GenInstrMsa3RF()
1411   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in GenInstrMsaVec()
1421   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in GenInstrMsaMI10()
1430   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in GenInstrMsa2R()
1439   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in GenInstrMsa2RF()
1449   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in GenInstrMsaBranch()
3392     DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));     \
3686   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in move_v()
3694   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in ctcmsa()
3702   DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));  in cfcmsa()