Lines Matching refs:MIPS_SIMD
81 supported_ |= 1u << MIPS_SIMD; in ProbeImpl()
89 supported_ |= 1u << MIPS_SIMD; in ProbeImpl()
91 if (cpu.has_msa()) supported_ |= 1u << MIPS_SIMD; in ProbeImpl()
1303 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaI8()
1312 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaI5()
1326 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaBit()
1335 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaI10()
1345 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsa3R()
1355 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaElm()
1365 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsa3RF()
1375 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaVec()
1385 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaMI10()
1394 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsa2R()
1403 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsa2RF()
1413 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaBranch()
3709 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); \
4012 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in move_v()
4020 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in ctcmsa()
4028 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in cfcmsa()