307   VRegister() : CPURegister(), lanes_(1) {}  in VRegister()
310         lanes_(1) {  in VRegister()
312     VIXL_ASSERT(IsPowerOf2(lanes_) && (lanes_ <= 16));  in VRegister()
315       : CPURegister(code, size, kVRegister), lanes_(lanes) {  in CPURegister()
316     VIXL_ASSERT(IsPowerOf2(lanes_) && (lanes_ <= 16));  in CPURegister()
320         lanes_(IsVectorFormat(format) ? LaneCountFromFormat(format) : 1) {  in VRegister()
321     VIXL_ASSERT(IsPowerOf2(lanes_) && (lanes_ <= 16));  in VRegister()
375   bool Is8B() const { return (Is64Bits() && (lanes_ == 8)); }  in Is8B()
376   bool Is16B() const { return (Is128Bits() && (lanes_ == 16)); }  in Is16B()
377   bool Is2H() const { return (Is32Bits() && (lanes_ == 2)); }  in Is2H()
378   bool Is4H() const { return (Is64Bits() && (lanes_ == 4)); }  in Is4H()
379   bool Is8H() const { return (Is128Bits() && (lanes_ == 8)); }  in Is8H()
380   bool Is2S() const { return (Is64Bits() && (lanes_ == 2)); }  in Is2S()
381   bool Is4S() const { return (Is128Bits() && (lanes_ == 4)); }  in Is4S()
382   bool Is1D() const { return (Is64Bits() && (lanes_ == 1)); }  in Is1D()
383   bool Is2D() const { return (Is128Bits() && (lanes_ == 2)); }  in Is2D()
410   int GetLanes() const { return lanes_; }  in GetLanes()
413   bool IsScalar() const { return lanes_ == 1; }  in IsScalar()
415   bool IsVector() const { return lanes_ > 1; }  in IsVector()
418     return (size_ == other.size_) && (lanes_ == other.lanes_);  in IsSameFormat()
421   unsigned GetLaneSizeInBytes() const { return GetSizeInBytes() / lanes_; }  in GetLaneSizeInBytes()
438   int lanes_;  variable