Lines Matching refs:IsSignallingNaN
11183 VIXL_ASSERT(IsSignallingNaN(s1)); in TEST()
11184 VIXL_ASSERT(IsSignallingNaN(s2)); in TEST()
11185 VIXL_ASSERT(IsSignallingNaN(sa)); in TEST()
11281 VIXL_ASSERT(IsSignallingNaN(s1)); in TEST()
11282 VIXL_ASSERT(IsSignallingNaN(s2)); in TEST()
11283 VIXL_ASSERT(IsSignallingNaN(sa)); in TEST()
11508 if (IsSignallingNaN(n)) { in MinMaxHelper()
11511 } else if (IsSignallingNaN(m)) { in MinMaxHelper()
11659 VIXL_ASSERT(IsSignallingNaN(snan)); in TEST()
11763 VIXL_ASSERT(IsSignallingNaN(snan)); in TEST()
11909 VIXL_ASSERT(IsSignallingNaN(snan)); in TEST()
17050 VIXL_ASSERT(IsSignallingNaN(sn)); in TEST()
17126 VIXL_ASSERT(IsSignallingNaN(sn)); in TEST()
17239 VIXL_ASSERT(IsSignallingNaN(sn)); in TEST()
17240 VIXL_ASSERT(IsSignallingNaN(sm)); in TEST()
17311 VIXL_ASSERT(IsSignallingNaN(sn)); in TEST()
17312 VIXL_ASSERT(IsSignallingNaN(sm)); in TEST()
17387 VIXL_ASSERT(IsSignallingNaN(sn)); in TEST()
17388 VIXL_ASSERT(IsSignallingNaN(sm)); in TEST()
17512 VIXL_ASSERT(IsSignallingNaN(sn)); in TEST()
17513 VIXL_ASSERT(IsSignallingNaN(sm)); in TEST()
17514 VIXL_ASSERT(IsSignallingNaN(sa)); in TEST()
17640 VIXL_ASSERT(IsSignallingNaN(sn)); in TEST()
17641 VIXL_ASSERT(IsSignallingNaN(sm)); in TEST()
17642 VIXL_ASSERT(IsSignallingNaN(sa)); in TEST()