# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" define void @load_s64_gpr(i64* %addr) { ret void } define void @load_s32_gpr(i32* %addr) { ret void } define void @load_s16_gpr_anyext(i16* %addr) { ret void } define void @load_s16_gpr(i16* %addr) { ret void } define void @load_s8_gpr_anyext(i8* %addr) { ret void } define void @load_s8_gpr(i8* %addr) { ret void } define void @load_fi_s64_gpr() { %ptr0 = alloca i64 ret void } define void @load_gep_128_s64_gpr(i64* %addr) { ret void } define void @load_gep_512_s32_gpr(i32* %addr) { ret void } define void @load_gep_64_s16_gpr(i16* %addr) { ret void } define void @load_gep_1_s8_gpr(i8* %addr) { ret void } define void @load_s64_fpr(i64* %addr) { ret void } define void @load_s32_fpr(i32* %addr) { ret void } define void @load_s16_fpr(i16* %addr) { ret void } define void @load_s8_fpr(i8* %addr) { ret void } define void @load_gep_8_s64_fpr(i64* %addr) { ret void } define void @load_gep_16_s32_fpr(i32* %addr) { ret void } define void @load_gep_64_s16_fpr(i16* %addr) { ret void } define void @load_gep_32_s8_fpr(i8* %addr) { ret void } define void @load_v2s32(i64 *%addr) { ret void } ... --- name: load_s64_gpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_s64_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load 8 from %ir.addr) ; CHECK: $x0 = COPY [[LDRXui]] %0(p0) = COPY $x0 %1(s64) = G_LOAD %0 :: (load 8 from %ir.addr) $x0 = COPY %1(s64) ... --- name: load_s32_gpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_s32_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load 4 from %ir.addr) ; CHECK: $w0 = COPY [[LDRWui]] %0(p0) = COPY $x0 %1(s32) = G_LOAD %0 :: (load 4 from %ir.addr) $w0 = COPY %1(s32) ... --- name: load_s16_gpr_anyext legalized: true regBankSelected: true body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_s16_gpr_anyext ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr) ; CHECK: $w0 = COPY [[LDRHHui]] %0:gpr(p0) = COPY $x0 %1:gpr(s32) = G_LOAD %0 :: (load 2 from %ir.addr) $w0 = COPY %1(s32) ... --- name: load_s16_gpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_s16_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr) ; CHECK: [[T0:%[0-9]+]]:gpr32all = COPY [[LDRHHui]] ; CHECK: $w0 = COPY [[T0]] %0(p0) = COPY $x0 %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr) %2:gpr(s32) = G_ANYEXT %1 $w0 = COPY %2(s32) ... --- name: load_s8_gpr_anyext legalized: true regBankSelected: true body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_s8_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr) ; CHECK: $w0 = COPY [[LDRBBui]] %0:gpr(p0) = COPY $x0 %1:gpr(s32) = G_LOAD %0 :: (load 1 from %ir.addr) $w0 = COPY %1(s32) ... --- name: load_s8_gpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_s8_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr) ; CHECK: [[T0:%[0-9]+]]:gpr32all = COPY [[LDRBBui]] ; CHECK: $w0 = COPY [[T0]] %0(p0) = COPY $x0 %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %2:gpr(s32) = G_ANYEXT %1 $w0 = COPY %2(s32) ... --- name: load_fi_s64_gpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } stack: - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_fi_s64_gpr ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui %stack.0.ptr0, 0 :: (load 8) ; CHECK: $x0 = COPY [[LDRXui]] %0(p0) = G_FRAME_INDEX %stack.0.ptr0 %1(s64) = G_LOAD %0 :: (load 8) $x0 = COPY %1(s64) ... --- name: load_gep_128_s64_gpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_gep_128_s64_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 16 :: (load 8 from %ir.addr) ; CHECK: $x0 = COPY [[LDRXui]] %0(p0) = COPY $x0 %1(s64) = G_CONSTANT i64 128 %2(p0) = G_GEP %0, %1 %3(s64) = G_LOAD %2 :: (load 8 from %ir.addr) $x0 = COPY %3 ... --- name: load_gep_512_s32_gpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_gep_512_s32_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 128 :: (load 4 from %ir.addr) ; CHECK: $w0 = COPY [[LDRWui]] %0(p0) = COPY $x0 %1(s64) = G_CONSTANT i64 512 %2(p0) = G_GEP %0, %1 %3(s32) = G_LOAD %2 :: (load 4 from %ir.addr) $w0 = COPY %3 ... --- name: load_gep_64_s16_gpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_gep_64_s16_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load 2 from %ir.addr) ; CHECK: [[T0:%[0-9]+]]:gpr32all = COPY [[LDRHHui]] ; CHECK: $w0 = COPY [[T0]] %0(p0) = COPY $x0 %1(s64) = G_CONSTANT i64 64 %2(p0) = G_GEP %0, %1 %3(s16) = G_LOAD %2 :: (load 2 from %ir.addr) %4:gpr(s32) = G_ANYEXT %3 $w0 = COPY %4 ... --- name: load_gep_1_s8_gpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_gep_1_s8_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load 1 from %ir.addr) ; CHECK: [[T0:%[0-9]+]]:gpr32all = COPY [[LDRBBui]] ; CHECK: $w0 = COPY [[T0]] %0(p0) = COPY $x0 %1(s64) = G_CONSTANT i64 1 %2(p0) = G_GEP %0, %1 %3(s8) = G_LOAD %2 :: (load 1 from %ir.addr) %4:gpr(s32) = G_ANYEXT %3 $w0 = COPY %4 ... --- name: load_s64_fpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: fpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_s64_fpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr) ; CHECK: $d0 = COPY [[LDRDui]] %0(p0) = COPY $x0 %1(s64) = G_LOAD %0 :: (load 8 from %ir.addr) $d0 = COPY %1(s64) ... --- name: load_s32_fpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: fpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_s32_fpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 :: (load 4 from %ir.addr) ; CHECK: $s0 = COPY [[LDRSui]] %0(p0) = COPY $x0 %1(s32) = G_LOAD %0 :: (load 4 from %ir.addr) $s0 = COPY %1(s32) ... --- name: load_s16_fpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: fpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_s16_fpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load 2 from %ir.addr) ; CHECK: $h0 = COPY [[LDRHui]] %0(p0) = COPY $x0 %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr) $h0 = COPY %1(s16) ... --- name: load_s8_fpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: fpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_s8_fpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load 1 from %ir.addr) ; CHECK: $b0 = COPY [[LDRBui]] %0(p0) = COPY $x0 %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr) $b0 = COPY %1(s8) ... --- name: load_gep_8_s64_fpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: fpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_gep_8_s64_fpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 1 :: (load 8 from %ir.addr) ; CHECK: $d0 = COPY [[LDRDui]] %0(p0) = COPY $x0 %1(s64) = G_CONSTANT i64 8 %2(p0) = G_GEP %0, %1 %3(s64) = G_LOAD %2 :: (load 8 from %ir.addr) $d0 = COPY %3 ... --- name: load_gep_16_s32_fpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: fpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_gep_16_s32_fpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 4 :: (load 4 from %ir.addr) ; CHECK: $s0 = COPY [[LDRSui]] %0(p0) = COPY $x0 %1(s64) = G_CONSTANT i64 16 %2(p0) = G_GEP %0, %1 %3(s32) = G_LOAD %2 :: (load 4 from %ir.addr) $s0 = COPY %3 ... --- name: load_gep_64_s16_fpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: fpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_gep_64_s16_fpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 32 :: (load 2 from %ir.addr) ; CHECK: $h0 = COPY [[LDRHui]] %0(p0) = COPY $x0 %1(s64) = G_CONSTANT i64 64 %2(p0) = G_GEP %0, %1 %3(s16) = G_LOAD %2 :: (load 2 from %ir.addr) $h0 = COPY %3 ... --- name: load_gep_32_s8_fpr legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: fpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_gep_32_s8_fpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 32 :: (load 1 from %ir.addr) ; CHECK: $b0 = COPY [[LDRBui]] %0(p0) = COPY $x0 %1(s64) = G_CONSTANT i64 32 %2(p0) = G_GEP %0, %1 %3(s8) = G_LOAD %2 :: (load 1 from %ir.addr) $b0 = COPY %3 ... --- name: load_v2s32 legalized: true regBankSelected: true registers: - { id: 0, class: gpr } - { id: 1, class: fpr } body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: load_v2s32 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr) ; CHECK: $d0 = COPY [[LDRDui]] %0(p0) = COPY $x0 %1(<2 x s32>) = G_LOAD %0 :: (load 8 from %ir.addr) $d0 = COPY %1(<2 x s32>) ...