1 /* 2 * Copyright (C) 2014 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_RUNTIME_ARCH_MIPS64_REGISTERS_MIPS64_H_ 18 #define ART_RUNTIME_ARCH_MIPS64_REGISTERS_MIPS64_H_ 19 20 #include <iosfwd> 21 22 #include "base/macros.h" 23 24 namespace art { 25 namespace mips64 { 26 27 enum GpuRegister { 28 ZERO = 0, 29 AT = 1, // Assembler temporary. 30 V0 = 2, // Values. 31 V1 = 3, 32 A0 = 4, // Arguments. 33 A1 = 5, 34 A2 = 6, 35 A3 = 7, 36 A4 = 8, 37 A5 = 9, 38 A6 = 10, 39 A7 = 11, 40 T0 = 12, // Temporaries. 41 T1 = 13, 42 T2 = 14, 43 T3 = 15, 44 S0 = 16, // Saved values. 45 S1 = 17, 46 S2 = 18, 47 S3 = 19, 48 S4 = 20, 49 S5 = 21, 50 S6 = 22, 51 S7 = 23, 52 T8 = 24, // More temporaries. 53 T9 = 25, 54 K0 = 26, // Reserved for trap handler. 55 K1 = 27, 56 GP = 28, // Global pointer. 57 SP = 29, // Stack pointer. 58 S8 = 30, // Saved value/frame pointer. 59 RA = 31, // Return address. 60 TR = S1, // ART Thread Register 61 TMP = T8, // scratch register (in addition to AT) 62 TMP2 = T3, // scratch register (in addition to AT, reserved for assembler) 63 kNumberOfGpuRegisters = 32, 64 kNoGpuRegister = -1 // Signals an illegal register. 65 }; 66 std::ostream& operator<<(std::ostream& os, const GpuRegister& rhs); 67 68 // Values for floating point registers. 69 enum FpuRegister { 70 F0 = 0, 71 F1 = 1, 72 F2 = 2, 73 F3 = 3, 74 F4 = 4, 75 F5 = 5, 76 F6 = 6, 77 F7 = 7, 78 F8 = 8, 79 F9 = 9, 80 F10 = 10, 81 F11 = 11, 82 F12 = 12, 83 F13 = 13, 84 F14 = 14, 85 F15 = 15, 86 F16 = 16, 87 F17 = 17, 88 F18 = 18, 89 F19 = 19, 90 F20 = 20, 91 F21 = 21, 92 F22 = 22, 93 F23 = 23, 94 F24 = 24, 95 F25 = 25, 96 F26 = 26, 97 F27 = 27, 98 F28 = 28, 99 F29 = 29, 100 F30 = 30, 101 F31 = 31, 102 FTMP = F8, // scratch register 103 FTMP2 = F9, // scratch register (in addition to FTMP, reserved for MSA instructions) 104 kNumberOfFpuRegisters = 32, 105 kNoFpuRegister = -1, 106 }; 107 std::ostream& operator<<(std::ostream& os, const FpuRegister& rhs); 108 109 // Values for vector registers. 110 enum VectorRegister { 111 W0 = 0, 112 W1 = 1, 113 W2 = 2, 114 W3 = 3, 115 W4 = 4, 116 W5 = 5, 117 W6 = 6, 118 W7 = 7, 119 W8 = 8, 120 W9 = 9, 121 W10 = 10, 122 W11 = 11, 123 W12 = 12, 124 W13 = 13, 125 W14 = 14, 126 W15 = 15, 127 W16 = 16, 128 W17 = 17, 129 W18 = 18, 130 W19 = 19, 131 W20 = 20, 132 W21 = 21, 133 W22 = 22, 134 W23 = 23, 135 W24 = 24, 136 W25 = 25, 137 W26 = 26, 138 W27 = 27, 139 W28 = 28, 140 W29 = 29, 141 W30 = 30, 142 W31 = 31, 143 kNumberOfVectorRegisters = 32, 144 kNoVectorRegister = -1, 145 }; 146 std::ostream& operator<<(std::ostream& os, const VectorRegister& rhs); 147 148 } // namespace mips64 149 } // namespace art 150 151 #endif // ART_RUNTIME_ARCH_MIPS64_REGISTERS_MIPS64_H_ 152