1 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This file implements the lowering of LLVM calls to machine code calls for
12 /// GlobalISel.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "ARMCallLowering.h"
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMISelLowering.h"
19 #include "ARMSubtarget.h"
20 #include "Utils/ARMBaseInfo.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
25 #include "llvm/CodeGen/GlobalISel/Utils.h"
26 #include "llvm/CodeGen/LowLevelType.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/TargetRegisterInfo.h"
35 #include "llvm/CodeGen/TargetSubtargetInfo.h"
36 #include "llvm/CodeGen/ValueTypes.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/Type.h"
42 #include "llvm/IR/Value.h"
43 #include "llvm/Support/Casting.h"
44 #include "llvm/Support/LowLevelTypeImpl.h"
45 #include "llvm/Support/MachineValueType.h"
46 #include <algorithm>
47 #include <cassert>
48 #include <cstdint>
49 #include <utility>
50
51 using namespace llvm;
52
ARMCallLowering(const ARMTargetLowering & TLI)53 ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
54 : CallLowering(&TLI) {}
55
isSupportedType(const DataLayout & DL,const ARMTargetLowering & TLI,Type * T)56 static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
57 Type *T) {
58 if (T->isArrayTy())
59 return true;
60
61 if (T->isStructTy()) {
62 // For now we only allow homogeneous structs that we can manipulate with
63 // G_MERGE_VALUES and G_UNMERGE_VALUES
64 auto StructT = cast<StructType>(T);
65 for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i)
66 if (StructT->getElementType(i) != StructT->getElementType(0))
67 return false;
68 return true;
69 }
70
71 EVT VT = TLI.getValueType(DL, T, true);
72 if (!VT.isSimple() || VT.isVector() ||
73 !(VT.isInteger() || VT.isFloatingPoint()))
74 return false;
75
76 unsigned VTSize = VT.getSimpleVT().getSizeInBits();
77
78 if (VTSize == 64)
79 // FIXME: Support i64 too
80 return VT.isFloatingPoint();
81
82 return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
83 }
84
85 namespace {
86
87 /// Helper class for values going out through an ABI boundary (used for handling
88 /// function return values and call parameters).
89 struct OutgoingValueHandler : public CallLowering::ValueHandler {
OutgoingValueHandler__anon894b28320111::OutgoingValueHandler90 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
91 MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
92 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
93
getStackAddress__anon894b28320111::OutgoingValueHandler94 unsigned getStackAddress(uint64_t Size, int64_t Offset,
95 MachinePointerInfo &MPO) override {
96 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
97 "Unsupported size");
98
99 LLT p0 = LLT::pointer(0, 32);
100 LLT s32 = LLT::scalar(32);
101 unsigned SPReg = MRI.createGenericVirtualRegister(p0);
102 MIRBuilder.buildCopy(SPReg, ARM::SP);
103
104 unsigned OffsetReg = MRI.createGenericVirtualRegister(s32);
105 MIRBuilder.buildConstant(OffsetReg, Offset);
106
107 unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
108 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
109
110 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
111 return AddrReg;
112 }
113
assignValueToReg__anon894b28320111::OutgoingValueHandler114 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
115 CCValAssign &VA) override {
116 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
117 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
118
119 assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
120 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
121
122 unsigned ExtReg = extendRegister(ValVReg, VA);
123 MIRBuilder.buildCopy(PhysReg, ExtReg);
124 MIB.addUse(PhysReg, RegState::Implicit);
125 }
126
assignValueToAddress__anon894b28320111::OutgoingValueHandler127 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
128 MachinePointerInfo &MPO, CCValAssign &VA) override {
129 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
130 "Unsupported size");
131
132 unsigned ExtReg = extendRegister(ValVReg, VA);
133 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
134 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
135 /* Alignment */ 0);
136 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
137 }
138
assignCustomValue__anon894b28320111::OutgoingValueHandler139 unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
140 ArrayRef<CCValAssign> VAs) override {
141 CCValAssign VA = VAs[0];
142 assert(VA.needsCustom() && "Value doesn't need custom handling");
143 assert(VA.getValVT() == MVT::f64 && "Unsupported type");
144
145 CCValAssign NextVA = VAs[1];
146 assert(NextVA.needsCustom() && "Value doesn't need custom handling");
147 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
148
149 assert(VA.getValNo() == NextVA.getValNo() &&
150 "Values belong to different arguments");
151
152 assert(VA.isRegLoc() && "Value should be in reg");
153 assert(NextVA.isRegLoc() && "Value should be in reg");
154
155 unsigned NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
156 MRI.createGenericVirtualRegister(LLT::scalar(32))};
157 MIRBuilder.buildUnmerge(NewRegs, Arg.Reg);
158
159 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
160 if (!IsLittle)
161 std::swap(NewRegs[0], NewRegs[1]);
162
163 assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
164 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
165
166 return 1;
167 }
168
assignArg__anon894b28320111::OutgoingValueHandler169 bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
170 CCValAssign::LocInfo LocInfo,
171 const CallLowering::ArgInfo &Info, CCState &State) override {
172 if (AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State))
173 return true;
174
175 StackSize =
176 std::max(StackSize, static_cast<uint64_t>(State.getNextStackOffset()));
177 return false;
178 }
179
180 MachineInstrBuilder &MIB;
181 uint64_t StackSize = 0;
182 };
183
184 } // end anonymous namespace
185
splitToValueTypes(const ArgInfo & OrigArg,SmallVectorImpl<ArgInfo> & SplitArgs,MachineFunction & MF,const SplitArgTy & PerformArgSplit) const186 void ARMCallLowering::splitToValueTypes(
187 const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs,
188 MachineFunction &MF, const SplitArgTy &PerformArgSplit) const {
189 const ARMTargetLowering &TLI = *getTLI<ARMTargetLowering>();
190 LLVMContext &Ctx = OrigArg.Ty->getContext();
191 const DataLayout &DL = MF.getDataLayout();
192 MachineRegisterInfo &MRI = MF.getRegInfo();
193 const Function &F = MF.getFunction();
194
195 SmallVector<EVT, 4> SplitVTs;
196 SmallVector<uint64_t, 4> Offsets;
197 ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
198
199 if (SplitVTs.size() == 1) {
200 // Even if there is no splitting to do, we still want to replace the
201 // original type (e.g. pointer type -> integer).
202 auto Flags = OrigArg.Flags;
203 unsigned OriginalAlignment = DL.getABITypeAlignment(OrigArg.Ty);
204 Flags.setOrigAlign(OriginalAlignment);
205 SplitArgs.emplace_back(OrigArg.Reg, SplitVTs[0].getTypeForEVT(Ctx), Flags,
206 OrigArg.IsFixed);
207 return;
208 }
209
210 unsigned FirstRegIdx = SplitArgs.size();
211 for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
212 EVT SplitVT = SplitVTs[i];
213 Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
214 auto Flags = OrigArg.Flags;
215
216 unsigned OriginalAlignment = DL.getABITypeAlignment(SplitTy);
217 Flags.setOrigAlign(OriginalAlignment);
218
219 bool NeedsConsecutiveRegisters =
220 TLI.functionArgumentNeedsConsecutiveRegisters(
221 SplitTy, F.getCallingConv(), F.isVarArg());
222 if (NeedsConsecutiveRegisters) {
223 Flags.setInConsecutiveRegs();
224 if (i == e - 1)
225 Flags.setInConsecutiveRegsLast();
226 }
227
228 SplitArgs.push_back(
229 ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*SplitTy, DL)),
230 SplitTy, Flags, OrigArg.IsFixed});
231 }
232
233 for (unsigned i = 0; i < Offsets.size(); ++i)
234 PerformArgSplit(SplitArgs[FirstRegIdx + i].Reg, Offsets[i] * 8);
235 }
236
237 /// Lower the return value for the already existing \p Ret. This assumes that
238 /// \p MIRBuilder's insertion point is correct.
lowerReturnVal(MachineIRBuilder & MIRBuilder,const Value * Val,unsigned VReg,MachineInstrBuilder & Ret) const239 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
240 const Value *Val, unsigned VReg,
241 MachineInstrBuilder &Ret) const {
242 if (!Val)
243 // Nothing to do here.
244 return true;
245
246 auto &MF = MIRBuilder.getMF();
247 const auto &F = MF.getFunction();
248
249 auto DL = MF.getDataLayout();
250 auto &TLI = *getTLI<ARMTargetLowering>();
251 if (!isSupportedType(DL, TLI, Val->getType()))
252 return false;
253
254 SmallVector<ArgInfo, 4> SplitVTs;
255 SmallVector<unsigned, 4> Regs;
256 ArgInfo RetInfo(VReg, Val->getType());
257 setArgFlags(RetInfo, AttributeList::ReturnIndex, DL, F);
258 splitToValueTypes(RetInfo, SplitVTs, MF, [&](unsigned Reg, uint64_t Offset) {
259 Regs.push_back(Reg);
260 });
261
262 if (Regs.size() > 1)
263 MIRBuilder.buildUnmerge(Regs, VReg);
264
265 CCAssignFn *AssignFn =
266 TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
267
268 OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn);
269 return handleAssignments(MIRBuilder, SplitVTs, RetHandler);
270 }
271
lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,unsigned VReg) const272 bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
273 const Value *Val, unsigned VReg) const {
274 assert(!Val == !VReg && "Return value without a vreg");
275
276 auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
277 unsigned Opcode = ST.getReturnOpcode();
278 auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
279
280 if (!lowerReturnVal(MIRBuilder, Val, VReg, Ret))
281 return false;
282
283 MIRBuilder.insertInstr(Ret);
284 return true;
285 }
286
287 namespace {
288
289 /// Helper class for values coming in through an ABI boundary (used for handling
290 /// formal arguments and call return values).
291 struct IncomingValueHandler : public CallLowering::ValueHandler {
IncomingValueHandler__anon894b28320311::IncomingValueHandler292 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
293 CCAssignFn AssignFn)
294 : ValueHandler(MIRBuilder, MRI, AssignFn) {}
295
getStackAddress__anon894b28320311::IncomingValueHandler296 unsigned getStackAddress(uint64_t Size, int64_t Offset,
297 MachinePointerInfo &MPO) override {
298 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
299 "Unsupported size");
300
301 auto &MFI = MIRBuilder.getMF().getFrameInfo();
302
303 int FI = MFI.CreateFixedObject(Size, Offset, true);
304 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
305
306 unsigned AddrReg =
307 MRI.createGenericVirtualRegister(LLT::pointer(MPO.getAddrSpace(), 32));
308 MIRBuilder.buildFrameIndex(AddrReg, FI);
309
310 return AddrReg;
311 }
312
assignValueToAddress__anon894b28320311::IncomingValueHandler313 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
314 MachinePointerInfo &MPO, CCValAssign &VA) override {
315 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
316 "Unsupported size");
317
318 if (VA.getLocInfo() == CCValAssign::SExt ||
319 VA.getLocInfo() == CCValAssign::ZExt) {
320 // If the value is zero- or sign-extended, its size becomes 4 bytes, so
321 // that's what we should load.
322 Size = 4;
323 assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
324
325 auto LoadVReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
326 buildLoad(LoadVReg, Addr, Size, /* Alignment */ 0, MPO);
327 MIRBuilder.buildTrunc(ValVReg, LoadVReg);
328 } else {
329 // If the value is not extended, a simple load will suffice.
330 buildLoad(ValVReg, Addr, Size, /* Alignment */ 0, MPO);
331 }
332 }
333
buildLoad__anon894b28320311::IncomingValueHandler334 void buildLoad(unsigned Val, unsigned Addr, uint64_t Size, unsigned Alignment,
335 MachinePointerInfo &MPO) {
336 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
337 MPO, MachineMemOperand::MOLoad, Size, Alignment);
338 MIRBuilder.buildLoad(Val, Addr, *MMO);
339 }
340
assignValueToReg__anon894b28320311::IncomingValueHandler341 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
342 CCValAssign &VA) override {
343 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
344 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
345
346 auto ValSize = VA.getValVT().getSizeInBits();
347 auto LocSize = VA.getLocVT().getSizeInBits();
348
349 assert(ValSize <= 64 && "Unsupported value size");
350 assert(LocSize <= 64 && "Unsupported location size");
351
352 markPhysRegUsed(PhysReg);
353 if (ValSize == LocSize) {
354 MIRBuilder.buildCopy(ValVReg, PhysReg);
355 } else {
356 assert(ValSize < LocSize && "Extensions not supported");
357
358 // We cannot create a truncating copy, nor a trunc of a physical register.
359 // Therefore, we need to copy the content of the physical register into a
360 // virtual one and then truncate that.
361 auto PhysRegToVReg =
362 MRI.createGenericVirtualRegister(LLT::scalar(LocSize));
363 MIRBuilder.buildCopy(PhysRegToVReg, PhysReg);
364 MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
365 }
366 }
367
assignCustomValue__anon894b28320311::IncomingValueHandler368 unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg,
369 ArrayRef<CCValAssign> VAs) override {
370 CCValAssign VA = VAs[0];
371 assert(VA.needsCustom() && "Value doesn't need custom handling");
372 assert(VA.getValVT() == MVT::f64 && "Unsupported type");
373
374 CCValAssign NextVA = VAs[1];
375 assert(NextVA.needsCustom() && "Value doesn't need custom handling");
376 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
377
378 assert(VA.getValNo() == NextVA.getValNo() &&
379 "Values belong to different arguments");
380
381 assert(VA.isRegLoc() && "Value should be in reg");
382 assert(NextVA.isRegLoc() && "Value should be in reg");
383
384 unsigned NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
385 MRI.createGenericVirtualRegister(LLT::scalar(32))};
386
387 assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
388 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
389
390 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
391 if (!IsLittle)
392 std::swap(NewRegs[0], NewRegs[1]);
393
394 MIRBuilder.buildMerge(Arg.Reg, NewRegs);
395
396 return 1;
397 }
398
399 /// Marking a physical register as used is different between formal
400 /// parameters, where it's a basic block live-in, and call returns, where it's
401 /// an implicit-def of the call instruction.
402 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
403 };
404
405 struct FormalArgHandler : public IncomingValueHandler {
FormalArgHandler__anon894b28320311::FormalArgHandler406 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
407 CCAssignFn AssignFn)
408 : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
409
markPhysRegUsed__anon894b28320311::FormalArgHandler410 void markPhysRegUsed(unsigned PhysReg) override {
411 MIRBuilder.getMBB().addLiveIn(PhysReg);
412 }
413 };
414
415 } // end anonymous namespace
416
lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<unsigned> VRegs) const417 bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
418 const Function &F,
419 ArrayRef<unsigned> VRegs) const {
420 auto &TLI = *getTLI<ARMTargetLowering>();
421 auto Subtarget = TLI.getSubtarget();
422
423 if (Subtarget->isThumb())
424 return false;
425
426 // Quick exit if there aren't any args
427 if (F.arg_empty())
428 return true;
429
430 if (F.isVarArg())
431 return false;
432
433 auto &MF = MIRBuilder.getMF();
434 auto &MBB = MIRBuilder.getMBB();
435 auto DL = MF.getDataLayout();
436
437 for (auto &Arg : F.args()) {
438 if (!isSupportedType(DL, TLI, Arg.getType()))
439 return false;
440 if (Arg.hasByValOrInAllocaAttr())
441 return false;
442 }
443
444 CCAssignFn *AssignFn =
445 TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
446
447 FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
448 AssignFn);
449
450 SmallVector<ArgInfo, 8> ArgInfos;
451 SmallVector<unsigned, 4> SplitRegs;
452 unsigned Idx = 0;
453 for (auto &Arg : F.args()) {
454 ArgInfo AInfo(VRegs[Idx], Arg.getType());
455 setArgFlags(AInfo, Idx + AttributeList::FirstArgIndex, DL, F);
456
457 SplitRegs.clear();
458
459 splitToValueTypes(AInfo, ArgInfos, MF, [&](unsigned Reg, uint64_t Offset) {
460 SplitRegs.push_back(Reg);
461 });
462
463 if (!SplitRegs.empty())
464 MIRBuilder.buildMerge(VRegs[Idx], SplitRegs);
465
466 Idx++;
467 }
468
469 if (!MBB.empty())
470 MIRBuilder.setInstr(*MBB.begin());
471
472 if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
473 return false;
474
475 // Move back to the end of the basic block.
476 MIRBuilder.setMBB(MBB);
477 return true;
478 }
479
480 namespace {
481
482 struct CallReturnHandler : public IncomingValueHandler {
CallReturnHandler__anon894b28320511::CallReturnHandler483 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
484 MachineInstrBuilder MIB, CCAssignFn *AssignFn)
485 : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
486
markPhysRegUsed__anon894b28320511::CallReturnHandler487 void markPhysRegUsed(unsigned PhysReg) override {
488 MIB.addDef(PhysReg, RegState::Implicit);
489 }
490
491 MachineInstrBuilder MIB;
492 };
493
494 } // end anonymous namespace
495
lowerCall(MachineIRBuilder & MIRBuilder,CallingConv::ID CallConv,const MachineOperand & Callee,const ArgInfo & OrigRet,ArrayRef<ArgInfo> OrigArgs) const496 bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
497 CallingConv::ID CallConv,
498 const MachineOperand &Callee,
499 const ArgInfo &OrigRet,
500 ArrayRef<ArgInfo> OrigArgs) const {
501 MachineFunction &MF = MIRBuilder.getMF();
502 const auto &TLI = *getTLI<ARMTargetLowering>();
503 const auto &DL = MF.getDataLayout();
504 const auto &STI = MF.getSubtarget<ARMSubtarget>();
505 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
506 MachineRegisterInfo &MRI = MF.getRegInfo();
507
508 if (STI.genLongCalls())
509 return false;
510
511 auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
512
513 // Create the call instruction so we can add the implicit uses of arg
514 // registers, but don't insert it yet.
515 bool isDirect = !Callee.isReg();
516 auto CallOpcode =
517 isDirect ? ARM::BL
518 : STI.hasV5TOps()
519 ? ARM::BLX
520 : STI.hasV4TOps() ? ARM::BX_CALL : ARM::BMOVPCRX_CALL;
521 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode)
522 .add(Callee)
523 .addRegMask(TRI->getCallPreservedMask(MF, CallConv));
524 if (Callee.isReg()) {
525 auto CalleeReg = Callee.getReg();
526 if (CalleeReg && !TRI->isPhysicalRegister(CalleeReg))
527 MIB->getOperand(0).setReg(constrainOperandRegClass(
528 MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
529 *MIB.getInstr(), MIB->getDesc(), Callee, 0));
530 }
531
532 SmallVector<ArgInfo, 8> ArgInfos;
533 for (auto Arg : OrigArgs) {
534 if (!isSupportedType(DL, TLI, Arg.Ty))
535 return false;
536
537 if (!Arg.IsFixed)
538 return false;
539
540 if (Arg.Flags.isByVal())
541 return false;
542
543 SmallVector<unsigned, 8> Regs;
544 splitToValueTypes(Arg, ArgInfos, MF, [&](unsigned Reg, uint64_t Offset) {
545 Regs.push_back(Reg);
546 });
547
548 if (Regs.size() > 1)
549 MIRBuilder.buildUnmerge(Regs, Arg.Reg);
550 }
551
552 auto ArgAssignFn = TLI.CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
553 OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
554 if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
555 return false;
556
557 // Now we can add the actual call instruction to the correct basic block.
558 MIRBuilder.insertInstr(MIB);
559
560 if (!OrigRet.Ty->isVoidTy()) {
561 if (!isSupportedType(DL, TLI, OrigRet.Ty))
562 return false;
563
564 ArgInfos.clear();
565 SmallVector<unsigned, 8> SplitRegs;
566 splitToValueTypes(OrigRet, ArgInfos, MF,
567 [&](unsigned Reg, uint64_t Offset) {
568 SplitRegs.push_back(Reg);
569 });
570
571 auto RetAssignFn = TLI.CCAssignFnForReturn(CallConv, /*IsVarArg=*/false);
572 CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
573 if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler))
574 return false;
575
576 if (!SplitRegs.empty()) {
577 // We have split the value and allocated each individual piece, now build
578 // it up again.
579 MIRBuilder.buildMerge(OrigRet.Reg, SplitRegs);
580 }
581 }
582
583 // We now know the size of the stack - update the ADJCALLSTACKDOWN
584 // accordingly.
585 CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
586
587 MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
588 .addImm(ArgHandler.StackSize)
589 .addImm(0)
590 .add(predOps(ARMCC::AL));
591
592 return true;
593 }
594