/external/u-boot/arch/sh/include/asm/ |
D | cpu_sh7763.h | 11 #define CCR 0xFF00001C macro
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D | cpu_sh7269.h | 6 #define CCR CCR1 macro
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D | cpu_sh7264.h | 6 #define CCR CCR1 macro
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D | cpu_sh7203.h | 6 #define CCR CCR1 macro
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D | cpu_sh7706.h | 9 #define CCR 0xFFFFFFEC macro
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D | cpu_sh7734.h | 11 #define CCR 0xFF00001C macro
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D | cpu_sh7710.h | 9 #define CCR 0xFFFFFFEC macro
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D | cpu_sh7785.h | 20 #define CCR 0xFF00001C macro
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D | cpu_sh7750.h | 28 #define CCR 0xFF00001C macro
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D | cpu_sh7723.h | 29 #define CCR 0xFF00001C macro
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D | cpu_sh7724.h | 29 #define CCR 0xFF00001C macro
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D | cpu_sh7720.h | 30 #define CCR 0xFFFFFFEC macro
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D | cpu_sh7757.h | 9 #define CCR 0xFF00001C macro
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D | cpu_sh7752.h | 9 #define CCR 0xFF00001C macro
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D | cpu_sh7753.h | 9 #define CCR 0xFF00001C macro
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D | cpu_sh7780.h | 28 #define CCR 0xFF00001C macro
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D | cpu_sh7722.h | 29 #define CCR 0xFF00001C macro
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMISelDAGToDAG.cpp | 2105 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectT2CMOVShiftOp() 2132 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectARMCMOVShiftOp() 2152 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectT2CMOVImmOp() 2183 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectARMCMOVImmOp() 2219 SDValue CCR = N->getOperand(3); in SelectCMOVOp() local
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D | ARMISelLowering.cpp | 2772 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local 2796 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local 2806 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local 2916 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond() local 2946 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local 2966 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local 3282 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftRightParts() local 3316 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftLeftParts() local
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 3564 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerXALUO() local 3595 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT() local 3630 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local 3698 SDValue TrueVal, SDValue ARMcc, SDValue CCR, in getCMOV() 3901 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local 3927 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local 4039 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond() local 4083 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local 4102 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local 4540 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftRightParts() local [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 4031 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO() local 4122 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT() local 4157 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local 4225 SDValue TrueVal, SDValue ARMcc, SDValue CCR, in getCMOV() 4510 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local 4540 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local 4647 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond() local 4696 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBRCOND() local 4750 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local 4759 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local [all …]
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/external/u-boot/arch/arm/include/asm/arch-imx/ |
D | imx-regs.h | 351 #define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ macro
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/external/u-boot/arch/arm/include/asm/arch-pxa/ |
D | pxa-regs.h | 2530 #define CCR 0x44000090 /* Cursor Control Register */ macro
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