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Searched defs:CCR (Results 1 – 23 of 23) sorted by relevance

/external/u-boot/arch/sh/include/asm/
Dcpu_sh7763.h11 #define CCR 0xFF00001C macro
Dcpu_sh7269.h6 #define CCR CCR1 macro
Dcpu_sh7264.h6 #define CCR CCR1 macro
Dcpu_sh7203.h6 #define CCR CCR1 macro
Dcpu_sh7706.h9 #define CCR 0xFFFFFFEC macro
Dcpu_sh7734.h11 #define CCR 0xFF00001C macro
Dcpu_sh7710.h9 #define CCR 0xFFFFFFEC macro
Dcpu_sh7785.h20 #define CCR 0xFF00001C macro
Dcpu_sh7750.h28 #define CCR 0xFF00001C macro
Dcpu_sh7723.h29 #define CCR 0xFF00001C macro
Dcpu_sh7724.h29 #define CCR 0xFF00001C macro
Dcpu_sh7720.h30 #define CCR 0xFFFFFFEC macro
Dcpu_sh7757.h9 #define CCR 0xFF00001C macro
Dcpu_sh7752.h9 #define CCR 0xFF00001C macro
Dcpu_sh7753.h9 #define CCR 0xFF00001C macro
Dcpu_sh7780.h28 #define CCR 0xFF00001C macro
Dcpu_sh7722.h29 #define CCR 0xFF00001C macro
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelDAGToDAG.cpp2105 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectT2CMOVShiftOp()
2132 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectARMCMOVShiftOp()
2152 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectT2CMOVImmOp()
2183 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectARMCMOVImmOp()
2219 SDValue CCR = N->getOperand(3); in SelectCMOVOp() local
DARMISelLowering.cpp2772 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local
2796 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
2806 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
2916 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond() local
2946 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
2966 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
3282 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftRightParts() local
3316 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftLeftParts() local
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp3564 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerXALUO() local
3595 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT() local
3630 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local
3698 SDValue TrueVal, SDValue ARMcc, SDValue CCR, in getCMOV()
3901 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
3927 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
4039 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond() local
4083 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
4102 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
4540 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftRightParts() local
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.cpp4031 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO() local
4122 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT() local
4157 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local
4225 SDValue TrueVal, SDValue ARMcc, SDValue CCR, in getCMOV()
4510 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
4540 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
4647 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond() local
4696 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBRCOND() local
4750 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
4759 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
[all …]
/external/u-boot/arch/arm/include/asm/arch-imx/
Dimx-regs.h351 #define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ macro
/external/u-boot/arch/arm/include/asm/arch-pxa/
Dpxa-regs.h2530 #define CCR 0x44000090 /* Cursor Control Register */ macro