1 //===- HexagonBaseInfo.h - Top level definitions for Hexagon ----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the Hexagon target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
18 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
19 
20 #include "HexagonDepITypes.h"
21 #include "MCTargetDesc/HexagonMCTargetDesc.h"
22 
23 namespace llvm {
24 
25 /// HexagonII - This namespace holds all of the target specific flags that
26 /// instruction info tracks.
27 namespace HexagonII {
28   unsigned const TypeCVI_FIRST = TypeCVI_4SLOT_MPY;
29   unsigned const TypeCVI_LAST = TypeCVI_VX_LATE;
30 
31   enum SubTarget {
32     HasV4SubT     = 0x3f,
33     HasV5SubT     = 0x3e,
34     HasV55SubT    = 0x3c,
35     HasV60SubT    = 0x38,
36   };
37 
38   enum AddrMode {
39     NoAddrMode     = 0,  // No addressing mode
40     Absolute       = 1,  // Absolute addressing mode
41     AbsoluteSet    = 2,  // Absolute set addressing mode
42     BaseImmOffset  = 3,  // Indirect with offset
43     BaseLongOffset = 4,  // Indirect with long offset
44     BaseRegOffset  = 5,  // Indirect with register offset
45     PostInc        = 6   // Post increment addressing mode
46   };
47 
48   enum MemAccessSize {
49     NoMemAccess = 0,
50     ByteAccess,
51     HalfWordAccess,
52     WordAccess,
53     DoubleWordAccess,
54     HVXVectorAccess
55   };
56 
57   // MCInstrDesc TSFlags
58   // *** Must match HexagonInstrFormat*.td ***
59   enum {
60     // This 5-bit field describes the insn type.
61     TypePos  = 0,
62     TypeMask = 0x3f,
63 
64     // Solo instructions.
65     SoloPos  = 6,
66     SoloMask = 0x1,
67     // Packed only with A or X-type instructions.
68     SoloAXPos  = 7,
69     SoloAXMask = 0x1,
70     // Only A-type instruction in first slot or nothing.
71     RestrictSlot1AOKPos  = 8,
72     RestrictSlot1AOKMask = 0x1,
73 
74     // Predicated instructions.
75     PredicatedPos  = 9,
76     PredicatedMask = 0x1,
77     PredicatedFalsePos  = 10,
78     PredicatedFalseMask = 0x1,
79     PredicatedNewPos  = 11,
80     PredicatedNewMask = 0x1,
81     PredicateLatePos  = 12,
82     PredicateLateMask = 0x1,
83 
84     // New-Value consumer instructions.
85     NewValuePos  = 13,
86     NewValueMask = 0x1,
87     // New-Value producer instructions.
88     hasNewValuePos  = 14,
89     hasNewValueMask = 0x1,
90     // Which operand consumes or produces a new value.
91     NewValueOpPos  = 15,
92     NewValueOpMask = 0x7,
93     // Stores that can become new-value stores.
94     mayNVStorePos  = 18,
95     mayNVStoreMask = 0x1,
96     // New-value store instructions.
97     NVStorePos  = 19,
98     NVStoreMask = 0x1,
99     // Loads that can become current-value loads.
100     mayCVLoadPos  = 20,
101     mayCVLoadMask = 0x1,
102     // Current-value load instructions.
103     CVLoadPos  = 21,
104     CVLoadMask = 0x1,
105 
106     // Extendable insns.
107     ExtendablePos  = 22,
108     ExtendableMask = 0x1,
109     // Insns must be extended.
110     ExtendedPos  = 23,
111     ExtendedMask = 0x1,
112     // Which operand may be extended.
113     ExtendableOpPos  = 24,
114     ExtendableOpMask = 0x7,
115     // Signed or unsigned range.
116     ExtentSignedPos  = 27,
117     ExtentSignedMask = 0x1,
118     // Number of bits of range before extending operand.
119     ExtentBitsPos  = 28,
120     ExtentBitsMask = 0x1f,
121     // Alignment power-of-two before extending operand.
122     ExtentAlignPos  = 33,
123     ExtentAlignMask = 0x3,
124 
125     CofMax1Pos = 35,
126     CofMax1Mask = 0x1,
127     CofRelax1Pos = 36,
128     CofRelax1Mask = 0x1,
129     CofRelax2Pos = 37,
130     CofRelax2Mask = 0x1,
131 
132     RestrictNoSlot1StorePos  = 38,
133     RestrictNoSlot1StoreMask = 0x1,
134 
135     // Addressing mode for load/store instructions.
136     AddrModePos  = 41,
137     AddrModeMask = 0x7,
138     // Access size for load/store instructions.
139     MemAccessSizePos = 44,
140     MemAccesSizeMask = 0xf,
141 
142     // Branch predicted taken.
143     TakenPos = 48,
144     TakenMask = 0x1,
145 
146     // Floating-point instructions.
147     FPPos  = 49,
148     FPMask = 0x1,
149 
150     // New-Value producer-2 instructions.
151     hasNewValuePos2  = 51,
152     hasNewValueMask2 = 0x1,
153     // Which operand consumes or produces a new value.
154     NewValueOpPos2  = 52,
155     NewValueOpMask2 = 0x7,
156 
157     // Accumulator instructions.
158     AccumulatorPos = 55,
159     AccumulatorMask = 0x1,
160 
161     // Complex XU, prevent xu competition by preferring slot3
162     PrefersSlot3Pos = 56,
163     PrefersSlot3Mask = 0x1,
164 
165     // v65
166     HasTmpDstPos = 59,
167     HasTmpDstMask = 0x1,
168 
169     CVINewPos = 61,
170     CVINewMask = 0x1
171   };
172 
173   // *** The code above must match HexagonInstrFormat*.td *** //
174 
175   // Hexagon specific MO operand flag mask.
176   enum HexagonMOTargetFlagVal {
177     // Hexagon-specific MachineOperand target flags.
178     //
179     // When chaning these, make sure to update
180     // getSerializableDirectMachineOperandTargetFlags and
181     // getSerializableBitmaskMachineOperandTargetFlags if needed.
182     MO_NO_FLAG,
183 
184     /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
185     /// Used for computing a global address for PIC compilations
186     MO_PCREL,
187 
188     /// MO_GOT - Indicates a GOT-relative relocation
189     MO_GOT,
190 
191     // Low or high part of a symbol.
192     MO_LO16, MO_HI16,
193 
194     // Offset from the base of the SDA.
195     MO_GPREL,
196 
197     // MO_GDGOT - indicates GOT relative relocation for TLS
198     // GeneralDynamic method
199     MO_GDGOT,
200 
201     // MO_GDPLT - indicates PLT relative relocation for TLS
202     // GeneralDynamic method
203     MO_GDPLT,
204 
205     // MO_IE - indicates non PIC relocation for TLS
206     // Initial Executable method
207     MO_IE,
208 
209     // MO_IEGOT - indicates PIC relocation for TLS
210     // Initial Executable method
211     MO_IEGOT,
212 
213     // MO_TPREL - indicates relocation for TLS
214     // local Executable method
215     MO_TPREL,
216 
217     // HMOTF_ConstExtended
218     // Addendum to above, indicates a const extended op
219     // Can be used as a mask.
220     HMOTF_ConstExtended = 0x80,
221 
222     // Union of all bitmasks (currently only HMOTF_ConstExtended).
223     MO_Bitmasks = HMOTF_ConstExtended
224   };
225 
226   // Hexagon Sub-instruction classes.
227   enum SubInstructionGroup {
228     HSIG_None = 0,
229     HSIG_L1,
230     HSIG_L2,
231     HSIG_S1,
232     HSIG_S2,
233     HSIG_A,
234     HSIG_Compound
235   };
236 
237   // Hexagon Compound classes.
238   enum CompoundGroup {
239     HCG_None = 0,
240     HCG_A,
241     HCG_B,
242     HCG_C
243   };
244 
245   enum InstParseBits {
246     INST_PARSE_MASK       = 0x0000c000,
247     INST_PARSE_PACKET_END = 0x0000c000,
248     INST_PARSE_LOOP_END   = 0x00008000,
249     INST_PARSE_NOT_END    = 0x00004000,
250     INST_PARSE_DUPLEX     = 0x00000000,
251     INST_PARSE_EXTENDER   = 0x00000000
252   };
253 
254   enum InstIClassBits : unsigned {
255     INST_ICLASS_MASK      = 0xf0000000,
256     INST_ICLASS_EXTENDER  = 0x00000000,
257     INST_ICLASS_J_1       = 0x10000000,
258     INST_ICLASS_J_2       = 0x20000000,
259     INST_ICLASS_LD_ST_1   = 0x30000000,
260     INST_ICLASS_LD_ST_2   = 0x40000000,
261     INST_ICLASS_J_3       = 0x50000000,
262     INST_ICLASS_CR        = 0x60000000,
263     INST_ICLASS_ALU32_1   = 0x70000000,
264     INST_ICLASS_XTYPE_1   = 0x80000000,
265     INST_ICLASS_LD        = 0x90000000,
266     INST_ICLASS_ST        = 0xa0000000,
267     INST_ICLASS_ALU32_2   = 0xb0000000,
268     INST_ICLASS_XTYPE_2   = 0xc0000000,
269     INST_ICLASS_XTYPE_3   = 0xd0000000,
270     INST_ICLASS_XTYPE_4   = 0xe0000000,
271     INST_ICLASS_ALU32_3   = 0xf0000000
272   };
273 
274   LLVM_ATTRIBUTE_UNUSED
getMemAccessSizeInBytes(MemAccessSize S)275   static unsigned getMemAccessSizeInBytes(MemAccessSize S) {
276     switch (S) {
277       case ByteAccess:        return 1;
278       case HalfWordAccess:    return 2;
279       case WordAccess:        return 4;
280       case DoubleWordAccess:  return 8;
281       default:                return 0;
282     }
283   }
284 } // end namespace HexagonII
285 
286 } // end namespace llvm
287 
288 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
289