1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
16 
17 #include "PPCFrameLowering.h"
18 #include "PPCISelLowering.h"
19 #include "PPCInstrInfo.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/MC/MCInstrItineraries.h"
25 #include <string>
26 
27 #define GET_SUBTARGETINFO_HEADER
28 #include "PPCGenSubtargetInfo.inc"
29 
30 // GCC #defines PPC on Linux but we use it as our namespace name
31 #undef PPC
32 
33 namespace llvm {
34 class StringRef;
35 
36 namespace PPC {
37   // -m directive values.
38   enum {
39     DIR_NONE,
40     DIR_32,
41     DIR_440,
42     DIR_601,
43     DIR_602,
44     DIR_603,
45     DIR_7400,
46     DIR_750,
47     DIR_970,
48     DIR_A2,
49     DIR_E500,
50     DIR_E500mc,
51     DIR_E5500,
52     DIR_PWR3,
53     DIR_PWR4,
54     DIR_PWR5,
55     DIR_PWR5X,
56     DIR_PWR6,
57     DIR_PWR6X,
58     DIR_PWR7,
59     DIR_PWR8,
60     DIR_PWR9,
61     DIR_64
62   };
63 }
64 
65 class GlobalValue;
66 class TargetMachine;
67 
68 class PPCSubtarget : public PPCGenSubtargetInfo {
69 public:
70   enum POPCNTDKind {
71     POPCNTD_Unavailable,
72     POPCNTD_Slow,
73     POPCNTD_Fast
74   };
75 
76 protected:
77   /// TargetTriple - What processor and OS we're targeting.
78   Triple TargetTriple;
79 
80   /// stackAlignment - The minimum alignment known to hold of the stack frame on
81   /// entry to the function and which must be maintained by every function.
82   unsigned StackAlignment;
83 
84   /// Selected instruction itineraries (one entry per itinerary class.)
85   InstrItineraryData InstrItins;
86 
87   /// Which cpu directive was used.
88   unsigned DarwinDirective;
89 
90   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
91   bool HasMFOCRF;
92   bool Has64BitSupport;
93   bool Use64BitRegs;
94   bool UseCRBits;
95   bool HasHardFloat;
96   bool IsPPC64;
97   bool HasAltivec;
98   bool HasFPU;
99   bool HasSPE;
100   bool HasQPX;
101   bool HasVSX;
102   bool HasP8Vector;
103   bool HasP8Altivec;
104   bool HasP8Crypto;
105   bool HasP9Vector;
106   bool HasP9Altivec;
107   bool HasFCPSGN;
108   bool HasFSQRT;
109   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
110   bool HasRecipPrec;
111   bool HasSTFIWX;
112   bool HasLFIWAX;
113   bool HasFPRND;
114   bool HasFPCVT;
115   bool HasISEL;
116   bool HasBPERMD;
117   bool HasExtDiv;
118   bool HasCMPB;
119   bool HasLDBRX;
120   bool IsBookE;
121   bool HasOnlyMSYNC;
122   bool IsE500;
123   bool IsPPC4xx;
124   bool IsPPC6xx;
125   bool FeatureMFTB;
126   bool DeprecatedDST;
127   bool HasLazyResolverStubs;
128   bool IsLittleEndian;
129   bool HasICBT;
130   bool HasInvariantFunctionDescriptors;
131   bool HasPartwordAtomics;
132   bool HasDirectMove;
133   bool HasHTM;
134   bool HasFusion;
135   bool HasFloat128;
136   bool IsISA3_0;
137   bool UseLongCalls;
138   bool SecurePlt;
139 
140   POPCNTDKind HasPOPCNTD;
141 
142   /// When targeting QPX running a stock PPC64 Linux kernel where the stack
143   /// alignment has not been changed, we need to keep the 16-byte alignment
144   /// of the stack.
145   bool IsQPXStackUnaligned;
146 
147   const PPCTargetMachine &TM;
148   PPCFrameLowering FrameLowering;
149   PPCInstrInfo InstrInfo;
150   PPCTargetLowering TLInfo;
151   SelectionDAGTargetInfo TSInfo;
152 
153 public:
154   /// This constructor initializes the data members to match that
155   /// of the specified triple.
156   ///
157   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
158                const PPCTargetMachine &TM);
159 
160   /// ParseSubtargetFeatures - Parses features string setting specified
161   /// subtarget options.  Definition of function is auto generated by tblgen.
162   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
163 
164   /// getStackAlignment - Returns the minimum alignment known to hold of the
165   /// stack frame on entry to the function and which must be maintained by every
166   /// function for this subtarget.
getStackAlignment()167   unsigned getStackAlignment() const { return StackAlignment; }
168 
169   /// getDarwinDirective - Returns the -m directive specified for the cpu.
170   ///
getDarwinDirective()171   unsigned getDarwinDirective() const { return DarwinDirective; }
172 
173   /// getInstrItins - Return the instruction itineraries based on subtarget
174   /// selection.
getInstrItineraryData()175   const InstrItineraryData *getInstrItineraryData() const override {
176     return &InstrItins;
177   }
178 
getFrameLowering()179   const PPCFrameLowering *getFrameLowering() const override {
180     return &FrameLowering;
181   }
getInstrInfo()182   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
getTargetLowering()183   const PPCTargetLowering *getTargetLowering() const override {
184     return &TLInfo;
185   }
getSelectionDAGInfo()186   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
187     return &TSInfo;
188   }
getRegisterInfo()189   const PPCRegisterInfo *getRegisterInfo() const override {
190     return &getInstrInfo()->getRegisterInfo();
191   }
getTargetMachine()192   const PPCTargetMachine &getTargetMachine() const { return TM; }
193 
194   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
195   /// so that we can use initializer lists for subtarget initialization.
196   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
197 
198 private:
199   void initializeEnvironment();
200   void initSubtargetFeatures(StringRef CPU, StringRef FS);
201 
202 public:
203   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
204   ///
205   bool isPPC64() const;
206 
207   /// has64BitSupport - Return true if the selected CPU supports 64-bit
208   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
has64BitSupport()209   bool has64BitSupport() const { return Has64BitSupport; }
210   // useSoftFloat - Return true if soft-float option is turned on.
useSoftFloat()211   bool useSoftFloat() const { return !HasHardFloat; }
212 
213   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
214   /// registers in 32-bit mode when possible.  This can only true if
215   /// has64BitSupport() returns true.
use64BitRegs()216   bool use64BitRegs() const { return Use64BitRegs; }
217 
218   /// useCRBits - Return true if we should store and manipulate i1 values in
219   /// the individual condition register bits.
useCRBits()220   bool useCRBits() const { return UseCRBits; }
221 
222   /// hasLazyResolverStub - Return true if accesses to the specified global have
223   /// to go through a dyld lazy resolution stub.  This means that an extra load
224   /// is required to get the address of the global.
225   bool hasLazyResolverStub(const GlobalValue *GV) const;
226 
227   // isLittleEndian - True if generating little-endian code
isLittleEndian()228   bool isLittleEndian() const { return IsLittleEndian; }
229 
230   // Specific obvious features.
hasFCPSGN()231   bool hasFCPSGN() const { return HasFCPSGN; }
hasFSQRT()232   bool hasFSQRT() const { return HasFSQRT; }
hasFRE()233   bool hasFRE() const { return HasFRE; }
hasFRES()234   bool hasFRES() const { return HasFRES; }
hasFRSQRTE()235   bool hasFRSQRTE() const { return HasFRSQRTE; }
hasFRSQRTES()236   bool hasFRSQRTES() const { return HasFRSQRTES; }
hasRecipPrec()237   bool hasRecipPrec() const { return HasRecipPrec; }
hasSTFIWX()238   bool hasSTFIWX() const { return HasSTFIWX; }
hasLFIWAX()239   bool hasLFIWAX() const { return HasLFIWAX; }
hasFPRND()240   bool hasFPRND() const { return HasFPRND; }
hasFPCVT()241   bool hasFPCVT() const { return HasFPCVT; }
hasAltivec()242   bool hasAltivec() const { return HasAltivec; }
hasSPE()243   bool hasSPE() const { return HasSPE; }
hasFPU()244   bool hasFPU() const { return HasFPU; }
hasQPX()245   bool hasQPX() const { return HasQPX; }
hasVSX()246   bool hasVSX() const { return HasVSX; }
hasP8Vector()247   bool hasP8Vector() const { return HasP8Vector; }
hasP8Altivec()248   bool hasP8Altivec() const { return HasP8Altivec; }
hasP8Crypto()249   bool hasP8Crypto() const { return HasP8Crypto; }
hasP9Vector()250   bool hasP9Vector() const { return HasP9Vector; }
hasP9Altivec()251   bool hasP9Altivec() const { return HasP9Altivec; }
hasMFOCRF()252   bool hasMFOCRF() const { return HasMFOCRF; }
hasISEL()253   bool hasISEL() const { return HasISEL; }
hasBPERMD()254   bool hasBPERMD() const { return HasBPERMD; }
hasExtDiv()255   bool hasExtDiv() const { return HasExtDiv; }
hasCMPB()256   bool hasCMPB() const { return HasCMPB; }
hasLDBRX()257   bool hasLDBRX() const { return HasLDBRX; }
isBookE()258   bool isBookE() const { return IsBookE; }
hasOnlyMSYNC()259   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
isPPC4xx()260   bool isPPC4xx() const { return IsPPC4xx; }
isPPC6xx()261   bool isPPC6xx() const { return IsPPC6xx; }
isSecurePlt()262   bool isSecurePlt() const {return SecurePlt; }
isE500()263   bool isE500() const { return IsE500; }
isFeatureMFTB()264   bool isFeatureMFTB() const { return FeatureMFTB; }
isDeprecatedDST()265   bool isDeprecatedDST() const { return DeprecatedDST; }
hasICBT()266   bool hasICBT() const { return HasICBT; }
hasInvariantFunctionDescriptors()267   bool hasInvariantFunctionDescriptors() const {
268     return HasInvariantFunctionDescriptors;
269   }
hasPartwordAtomics()270   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
hasDirectMove()271   bool hasDirectMove() const { return HasDirectMove; }
272 
isQPXStackUnaligned()273   bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
getPlatformStackAlignment()274   unsigned getPlatformStackAlignment() const {
275     if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
276       return 32;
277 
278     return 16;
279   }
280 
281   // DarwinABI has a 224-byte red zone. PPC32 SVR4ABI(Non-DarwinABI) has no
282   // red zone and PPC64 SVR4ABI has a 288-byte red zone.
getRedZoneSize()283   unsigned  getRedZoneSize() const {
284     return isDarwinABI() ? 224 : (isPPC64() ? 288 : 0);
285   }
286 
hasHTM()287   bool hasHTM() const { return HasHTM; }
hasFusion()288   bool hasFusion() const { return HasFusion; }
hasFloat128()289   bool hasFloat128() const { return HasFloat128; }
isISA3_0()290   bool isISA3_0() const { return IsISA3_0; }
useLongCalls()291   bool useLongCalls() const { return UseLongCalls; }
needsSwapsForVSXMemOps()292   bool needsSwapsForVSXMemOps() const {
293     return hasVSX() && isLittleEndian() && !hasP9Vector();
294   }
295 
hasPOPCNTD()296   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
297 
getTargetTriple()298   const Triple &getTargetTriple() const { return TargetTriple; }
299 
300   /// isDarwin - True if this is any darwin platform.
isDarwin()301   bool isDarwin() const { return TargetTriple.isMacOSX(); }
302   /// isBGQ - True if this is a BG/Q platform.
isBGQ()303   bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
304 
isTargetELF()305   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
isTargetMachO()306   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
isTargetLinux()307   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
308 
isDarwinABI()309   bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
isSVR4ABI()310   bool isSVR4ABI() const { return !isDarwinABI(); }
311   bool isELFv2ABI() const;
312 
313   /// Originally, this function return hasISEL(). Now we always enable it,
314   /// but may expand the ISEL instruction later.
enableEarlyIfConversion()315   bool enableEarlyIfConversion() const override { return true; }
316 
317   // Scheduling customization.
318   bool enableMachineScheduler() const override;
319   // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
320   bool enablePostRAScheduler() const override;
321   AntiDepBreakMode getAntiDepBreakMode() const override;
322   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
323 
324   void overrideSchedPolicy(MachineSchedPolicy &Policy,
325                            unsigned NumRegionInstrs) const override;
326   bool useAA() const override;
327 
328   bool enableSubRegLiveness() const override;
329 
330   /// classifyGlobalReference - Classify a global variable reference for the
331   /// current subtarget accourding to how we should reference it.
332   unsigned char classifyGlobalReference(const GlobalValue *GV) const;
333 
isXRaySupported()334   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
335 };
336 } // End llvm namespace
337 
338 #endif
339