1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 17 18 #include "MCTargetDesc/MipsABIInfo.h" 19 #include "MCTargetDesc/MipsBaseInfo.h" 20 #include "MCTargetDesc/MipsMCTargetDesc.h" 21 #include "Mips.h" 22 #include "llvm/CodeGen/CallingConvLower.h" 23 #include "llvm/CodeGen/ISDOpcodes.h" 24 #include "llvm/CodeGen/MachineMemOperand.h" 25 #include "llvm/CodeGen/SelectionDAG.h" 26 #include "llvm/CodeGen/SelectionDAGNodes.h" 27 #include "llvm/CodeGen/TargetLowering.h" 28 #include "llvm/CodeGen/ValueTypes.h" 29 #include "llvm/IR/CallingConv.h" 30 #include "llvm/IR/InlineAsm.h" 31 #include "llvm/IR/Type.h" 32 #include "llvm/Support/MachineValueType.h" 33 #include "llvm/Target/TargetMachine.h" 34 #include <algorithm> 35 #include <cassert> 36 #include <deque> 37 #include <string> 38 #include <utility> 39 #include <vector> 40 41 namespace llvm { 42 43 class Argument; 44 class CCState; 45 class CCValAssign; 46 class FastISel; 47 class FunctionLoweringInfo; 48 class MachineBasicBlock; 49 class MachineFrameInfo; 50 class MachineInstr; 51 class MipsCCState; 52 class MipsFunctionInfo; 53 class MipsSubtarget; 54 class MipsTargetMachine; 55 class TargetLibraryInfo; 56 class TargetRegisterClass; 57 58 namespace MipsISD { 59 60 enum NodeType : unsigned { 61 // Start the numbering from where ISD NodeType finishes. 62 FIRST_NUMBER = ISD::BUILTIN_OP_END, 63 64 // Jump and link (call) 65 JmpLink, 66 67 // Tail call 68 TailCall, 69 70 // Get the Highest (63-48) 16 bits from a 64-bit immediate 71 Highest, 72 73 // Get the Higher (47-32) 16 bits from a 64-bit immediate 74 Higher, 75 76 // Get the High 16 bits from a 32/64-bit immediate 77 // No relation with Mips Hi register 78 Hi, 79 80 // Get the Lower 16 bits from a 32/64-bit immediate 81 // No relation with Mips Lo register 82 Lo, 83 84 // Get the High 16 bits from a 32 bit immediate for accessing the GOT. 85 GotHi, 86 87 // Get the High 16 bits from a 32-bit immediate for accessing TLS. 88 TlsHi, 89 90 // Handle gp_rel (small data/bss sections) relocation. 91 GPRel, 92 93 // Thread Pointer 94 ThreadPointer, 95 96 // Vector Floating Point Multiply and Subtract 97 FMS, 98 99 // Floating Point Branch Conditional 100 FPBrcond, 101 102 // Floating Point Compare 103 FPCmp, 104 105 // Floating point select 106 FSELECT, 107 108 // Node used to generate an MTC1 i32 to f64 instruction 109 MTC1_D64, 110 111 // Floating Point Conditional Moves 112 CMovFP_T, 113 CMovFP_F, 114 115 // FP-to-int truncation node. 116 TruncIntFP, 117 118 // Return 119 Ret, 120 121 // Interrupt, exception, error trap Return 122 ERet, 123 124 // Software Exception Return. 125 EH_RETURN, 126 127 // Node used to extract integer from accumulator. 128 MFHI, 129 MFLO, 130 131 // Node used to insert integers to accumulator. 132 MTLOHI, 133 134 // Mult nodes. 135 Mult, 136 Multu, 137 138 // MAdd/Sub nodes 139 MAdd, 140 MAddu, 141 MSub, 142 MSubu, 143 144 // DivRem(u) 145 DivRem, 146 DivRemU, 147 DivRem16, 148 DivRemU16, 149 150 BuildPairF64, 151 ExtractElementF64, 152 153 Wrapper, 154 155 DynAlloc, 156 157 Sync, 158 159 Ext, 160 Ins, 161 CIns, 162 163 // EXTR.W instrinsic nodes. 164 EXTP, 165 EXTPDP, 166 EXTR_S_H, 167 EXTR_W, 168 EXTR_R_W, 169 EXTR_RS_W, 170 SHILO, 171 MTHLIP, 172 173 // DPA.W intrinsic nodes. 174 MULSAQ_S_W_PH, 175 MAQ_S_W_PHL, 176 MAQ_S_W_PHR, 177 MAQ_SA_W_PHL, 178 MAQ_SA_W_PHR, 179 DPAU_H_QBL, 180 DPAU_H_QBR, 181 DPSU_H_QBL, 182 DPSU_H_QBR, 183 DPAQ_S_W_PH, 184 DPSQ_S_W_PH, 185 DPAQ_SA_L_W, 186 DPSQ_SA_L_W, 187 DPA_W_PH, 188 DPS_W_PH, 189 DPAQX_S_W_PH, 190 DPAQX_SA_W_PH, 191 DPAX_W_PH, 192 DPSX_W_PH, 193 DPSQX_S_W_PH, 194 DPSQX_SA_W_PH, 195 MULSA_W_PH, 196 197 MULT, 198 MULTU, 199 MADD_DSP, 200 MADDU_DSP, 201 MSUB_DSP, 202 MSUBU_DSP, 203 204 // DSP shift nodes. 205 SHLL_DSP, 206 SHRA_DSP, 207 SHRL_DSP, 208 209 // DSP setcc and select_cc nodes. 210 SETCC_DSP, 211 SELECT_CC_DSP, 212 213 // Vector comparisons. 214 // These take a vector and return a boolean. 215 VALL_ZERO, 216 VANY_ZERO, 217 VALL_NONZERO, 218 VANY_NONZERO, 219 220 // These take a vector and return a vector bitmask. 221 VCEQ, 222 VCLE_S, 223 VCLE_U, 224 VCLT_S, 225 VCLT_U, 226 227 // Vector Shuffle with mask as an operand 228 VSHF, // Generic shuffle 229 SHF, // 4-element set shuffle. 230 ILVEV, // Interleave even elements 231 ILVOD, // Interleave odd elements 232 ILVL, // Interleave left elements 233 ILVR, // Interleave right elements 234 PCKEV, // Pack even elements 235 PCKOD, // Pack odd elements 236 237 // Vector Lane Copy 238 INSVE, // Copy element from one vector to another 239 240 // Combined (XOR (OR $a, $b), -1) 241 VNOR, 242 243 // Extended vector element extraction 244 VEXTRACT_SEXT_ELT, 245 VEXTRACT_ZEXT_ELT, 246 247 // Load/Store Left/Right nodes. 248 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 249 LWR, 250 SWL, 251 SWR, 252 LDL, 253 LDR, 254 SDL, 255 SDR 256 }; 257 258 } // ene namespace MipsISD 259 260 //===--------------------------------------------------------------------===// 261 // TargetLowering Implementation 262 //===--------------------------------------------------------------------===// 263 264 class MipsTargetLowering : public TargetLowering { 265 bool isMicroMips; 266 267 public: 268 explicit MipsTargetLowering(const MipsTargetMachine &TM, 269 const MipsSubtarget &STI); 270 271 static const MipsTargetLowering *create(const MipsTargetMachine &TM, 272 const MipsSubtarget &STI); 273 274 /// createFastISel - This method returns a target specific FastISel object, 275 /// or null if the target does not support "fast" ISel. 276 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 277 const TargetLibraryInfo *libInfo) const override; 278 getScalarShiftAmountTy(const DataLayout &,EVT)279 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 280 return MVT::i32; 281 } 282 283 EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, 284 ISD::NodeType) const override; 285 286 bool isCheapToSpeculateCttz() const override; 287 bool isCheapToSpeculateCtlz() const override; 288 289 /// Return the register type for a given MVT, ensuring vectors are treated 290 /// as a series of gpr sized integers. 291 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 292 EVT VT) const override; 293 294 /// Return the number of registers for a given MVT, ensuring vectors are 295 /// treated as a series of gpr sized integers. 296 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 297 CallingConv::ID CC, 298 EVT VT) const override; 299 300 /// Break down vectors to the correct number of gpr sized integers. 301 unsigned getVectorTypeBreakdownForCallingConv( 302 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 303 unsigned &NumIntermediates, MVT &RegisterVT) const override; 304 305 /// Return the correct alignment for the current calling convention. getABIAlignmentForCallingConv(Type * ArgTy,DataLayout DL)306 unsigned getABIAlignmentForCallingConv(Type *ArgTy, 307 DataLayout DL) const override { 308 if (ArgTy->isVectorTy()) 309 return std::min(DL.getABITypeAlignment(ArgTy), 8U); 310 return DL.getABITypeAlignment(ArgTy); 311 } 312 getExtendForAtomicOps()313 ISD::NodeType getExtendForAtomicOps() const override { 314 return ISD::SIGN_EXTEND; 315 } 316 317 void LowerOperationWrapper(SDNode *N, 318 SmallVectorImpl<SDValue> &Results, 319 SelectionDAG &DAG) const override; 320 321 /// LowerOperation - Provide custom lowering hooks for some operations. 322 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 323 324 /// ReplaceNodeResults - Replace the results of node with an illegal result 325 /// type with new values built out of custom code. 326 /// 327 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 328 SelectionDAG &DAG) const override; 329 330 /// getTargetNodeName - This method returns the name of a target specific 331 // DAG node. 332 const char *getTargetNodeName(unsigned Opcode) const override; 333 334 /// getSetCCResultType - get the ISD::SETCC result ValueType 335 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 336 EVT VT) const override; 337 338 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 339 340 MachineBasicBlock * 341 EmitInstrWithCustomInserter(MachineInstr &MI, 342 MachineBasicBlock *MBB) const override; 343 344 void HandleByVal(CCState *, unsigned &, unsigned) const override; 345 346 unsigned getRegisterByName(const char* RegName, EVT VT, 347 SelectionDAG &DAG) const override; 348 349 /// If a physical register, this returns the register that receives the 350 /// exception address on entry to an EH pad. 351 unsigned getExceptionPointerRegister(const Constant * PersonalityFn)352 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 353 return ABI.IsN64() ? Mips::A0_64 : Mips::A0; 354 } 355 356 /// If a physical register, this returns the register that receives the 357 /// exception typeid on entry to a landing pad. 358 unsigned getExceptionSelectorRegister(const Constant * PersonalityFn)359 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 360 return ABI.IsN64() ? Mips::A1_64 : Mips::A1; 361 } 362 363 /// Returns true if a cast between SrcAS and DestAS is a noop. isNoopAddrSpaceCast(unsigned SrcAS,unsigned DestAS)364 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 365 // Mips doesn't have any special address spaces so we just reserve 366 // the first 256 for software use (e.g. OpenCL) and treat casts 367 // between them as noops. 368 return SrcAS < 256 && DestAS < 256; 369 } 370 isJumpTableRelative()371 bool isJumpTableRelative() const override { 372 return getTargetMachine().isPositionIndependent(); 373 } 374 375 CCAssignFn *CCAssignFnForCall() const; 376 377 CCAssignFn *CCAssignFnForReturn() const; 378 379 protected: 380 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 381 382 // This method creates the following nodes, which are necessary for 383 // computing a local symbol's address: 384 // 385 // (add (load (wrapper $gp, %got(sym)), %lo(sym)) 386 template <class NodeTy> getAddrLocal(NodeTy * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG,bool IsN32OrN64)387 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, 388 bool IsN32OrN64) const { 389 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 390 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 391 getTargetNode(N, Ty, DAG, GOTFlag)); 392 SDValue Load = 393 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 394 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 395 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 396 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, 397 getTargetNode(N, Ty, DAG, LoFlag)); 398 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 399 } 400 401 // This method creates the following nodes, which are necessary for 402 // computing a global symbol's address: 403 // 404 // (load (wrapper $gp, %got(sym))) 405 template <class NodeTy> getAddrGlobal(NodeTy * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG,unsigned Flag,SDValue Chain,const MachinePointerInfo & PtrInfo)406 SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, 407 unsigned Flag, SDValue Chain, 408 const MachinePointerInfo &PtrInfo) const { 409 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 410 getTargetNode(N, Ty, DAG, Flag)); 411 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo); 412 } 413 414 // This method creates the following nodes, which are necessary for 415 // computing a global symbol's address in large-GOT mode: 416 // 417 // (load (wrapper (add %hi(sym), $gp), %lo(sym))) 418 template <class NodeTy> getAddrGlobalLargeGOT(NodeTy * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG,unsigned HiFlag,unsigned LoFlag,SDValue Chain,const MachinePointerInfo & PtrInfo)419 SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, 420 SelectionDAG &DAG, unsigned HiFlag, 421 unsigned LoFlag, SDValue Chain, 422 const MachinePointerInfo &PtrInfo) const { 423 SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty, 424 getTargetNode(N, Ty, DAG, HiFlag)); 425 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); 426 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 427 getTargetNode(N, Ty, DAG, LoFlag)); 428 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo); 429 } 430 431 // This method creates the following nodes, which are necessary for 432 // computing a symbol's address in non-PIC mode: 433 // 434 // (add %hi(sym), %lo(sym)) 435 // 436 // This method covers O32, N32 and N64 in sym32 mode. 437 template <class NodeTy> getAddrNonPIC(NodeTy * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG)438 SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, 439 SelectionDAG &DAG) const { 440 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); 441 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); 442 return DAG.getNode(ISD::ADD, DL, Ty, 443 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 444 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 445 } 446 447 // This method creates the following nodes, which are necessary for 448 // computing a symbol's address in non-PIC mode for N64. 449 // 450 // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)), 451 // 16), %lo(%sym)) 452 // 453 // FIXME: This method is not efficent for (micro)MIPS64R6. 454 template <class NodeTy> getAddrNonPICSym64(NodeTy * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG)455 SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, 456 SelectionDAG &DAG) const { 457 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); 458 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); 459 460 SDValue Highest = 461 DAG.getNode(MipsISD::Highest, DL, Ty, 462 getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST)); 463 SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER); 464 SDValue HigherPart = 465 DAG.getNode(ISD::ADD, DL, Ty, Highest, 466 DAG.getNode(MipsISD::Higher, DL, Ty, Higher)); 467 SDValue Cst = DAG.getConstant(16, DL, MVT::i32); 468 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst); 469 SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift, 470 DAG.getNode(MipsISD::Hi, DL, Ty, Hi)); 471 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst); 472 473 return DAG.getNode(ISD::ADD, DL, Ty, Shift2, 474 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 475 } 476 477 // This method creates the following nodes, which are necessary for 478 // computing a symbol's address using gp-relative addressing: 479 // 480 // (add $gp, %gp_rel(sym)) 481 template <class NodeTy> getAddrGPRel(NodeTy * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG,bool IsN64)482 SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, 483 SelectionDAG &DAG, bool IsN64) const { 484 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL); 485 return DAG.getNode( 486 ISD::ADD, DL, Ty, 487 DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty), 488 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel)); 489 } 490 491 /// This function fills Ops, which is the list of operands that will later 492 /// be used when a function call node is created. It also generates 493 /// copyToReg nodes to set up argument registers. 494 virtual void 495 getOpndList(SmallVectorImpl<SDValue> &Ops, 496 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 497 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 498 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 499 SDValue Chain) const; 500 501 protected: 502 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 503 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 504 505 // Subtarget Info 506 const MipsSubtarget &Subtarget; 507 // Cache the ABI from the TargetMachine, we use it everywhere. 508 const MipsABIInfo &ABI; 509 510 private: 511 // Create a TargetGlobalAddress node. 512 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 513 unsigned Flag) const; 514 515 // Create a TargetExternalSymbol node. 516 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, 517 unsigned Flag) const; 518 519 // Create a TargetBlockAddress node. 520 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 521 unsigned Flag) const; 522 523 // Create a TargetJumpTable node. 524 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 525 unsigned Flag) const; 526 527 // Create a TargetConstantPool node. 528 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 529 unsigned Flag) const; 530 531 // Lower Operand helpers 532 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 533 CallingConv::ID CallConv, bool isVarArg, 534 const SmallVectorImpl<ISD::InputArg> &Ins, 535 const SDLoc &dl, SelectionDAG &DAG, 536 SmallVectorImpl<SDValue> &InVals, 537 TargetLowering::CallLoweringInfo &CLI) const; 538 539 // Lower Operand specifics 540 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 541 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 542 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 543 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 544 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 545 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 546 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 547 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 548 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 549 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const; 550 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 551 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 552 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 553 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 554 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 555 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 556 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 557 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 558 bool IsSRA) const; 559 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const; 560 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 561 562 /// isEligibleForTailCallOptimization - Check whether the call is eligible 563 /// for tail call optimization. 564 virtual bool 565 isEligibleForTailCallOptimization(const CCState &CCInfo, 566 unsigned NextStackOffset, 567 const MipsFunctionInfo &FI) const = 0; 568 569 /// copyByValArg - Copy argument registers which were used to pass a byval 570 /// argument to the stack. Create a stack frame object for the byval 571 /// argument. 572 void copyByValRegs(SDValue Chain, const SDLoc &DL, 573 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 574 const ISD::ArgFlagsTy &Flags, 575 SmallVectorImpl<SDValue> &InVals, 576 const Argument *FuncArg, unsigned FirstReg, 577 unsigned LastReg, const CCValAssign &VA, 578 MipsCCState &State) const; 579 580 /// passByValArg - Pass a byval argument in registers or on stack. 581 void passByValArg(SDValue Chain, const SDLoc &DL, 582 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 583 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 584 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, 585 unsigned FirstReg, unsigned LastReg, 586 const ISD::ArgFlagsTy &Flags, bool isLittle, 587 const CCValAssign &VA) const; 588 589 /// writeVarArgRegs - Write variable function arguments passed in registers 590 /// to the stack. Also create a stack frame object for the first variable 591 /// argument. 592 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain, 593 const SDLoc &DL, SelectionDAG &DAG, 594 CCState &State) const; 595 596 SDValue 597 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 598 const SmallVectorImpl<ISD::InputArg> &Ins, 599 const SDLoc &dl, SelectionDAG &DAG, 600 SmallVectorImpl<SDValue> &InVals) const override; 601 602 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 603 SDValue Arg, const SDLoc &DL, bool IsTailCall, 604 SelectionDAG &DAG) const; 605 606 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 607 SmallVectorImpl<SDValue> &InVals) const override; 608 609 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 610 bool isVarArg, 611 const SmallVectorImpl<ISD::OutputArg> &Outs, 612 LLVMContext &Context) const override; 613 614 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 615 const SmallVectorImpl<ISD::OutputArg> &Outs, 616 const SmallVectorImpl<SDValue> &OutVals, 617 const SDLoc &dl, SelectionDAG &DAG) const override; 618 619 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 620 const SDLoc &DL, SelectionDAG &DAG) const; 621 622 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 623 624 // Inline asm support 625 ConstraintType getConstraintType(StringRef Constraint) const override; 626 627 /// Examine constraint string and operand type and determine a weight value. 628 /// The operand object must already have been set up with the operand type. 629 ConstraintWeight getSingleConstraintMatchWeight( 630 AsmOperandInfo &info, const char *constraint) const override; 631 632 /// This function parses registers that appear in inline-asm constraints. 633 /// It returns pair (0, 0) on failure. 634 std::pair<unsigned, const TargetRegisterClass *> 635 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const; 636 637 std::pair<unsigned, const TargetRegisterClass *> 638 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 639 StringRef Constraint, MVT VT) const override; 640 641 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 642 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 643 /// true it means one of the asm constraint of the inline asm instruction 644 /// being processed is 'm'. 645 void LowerAsmOperandForConstraint(SDValue Op, 646 std::string &Constraint, 647 std::vector<SDValue> &Ops, 648 SelectionDAG &DAG) const override; 649 650 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode)651 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 652 if (ConstraintCode == "R") 653 return InlineAsm::Constraint_R; 654 else if (ConstraintCode == "ZC") 655 return InlineAsm::Constraint_ZC; 656 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 657 } 658 659 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 660 Type *Ty, unsigned AS, 661 Instruction *I = nullptr) const override; 662 663 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 664 665 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 666 unsigned SrcAlign, 667 bool IsMemset, bool ZeroMemset, 668 bool MemcpyStrSrc, 669 MachineFunction &MF) const override; 670 671 /// isFPImmLegal - Returns true if the target can instruction select the 672 /// specified FP immediate natively. If false, the legalizer will 673 /// materialize the FP immediate as a load from a constant pool. 674 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 675 676 unsigned getJumpTableEncoding() const override; 677 bool useSoftFloat() const override; 678 shouldInsertFencesForAtomic(const Instruction * I)679 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 680 return true; 681 } 682 683 /// Emit a sign-extension using sll/sra, seb, or seh appropriately. 684 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI, 685 MachineBasicBlock *BB, 686 unsigned Size, unsigned DstReg, 687 unsigned SrcRec) const; 688 689 MachineBasicBlock *emitAtomicBinary(MachineInstr &MI, 690 MachineBasicBlock *BB) const; 691 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI, 692 MachineBasicBlock *BB, 693 unsigned Size) const; 694 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI, 695 MachineBasicBlock *BB) const; 696 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI, 697 MachineBasicBlock *BB, 698 unsigned Size) const; 699 MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const; 700 MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB, 701 bool isFPCmp, unsigned Opc) const; 702 }; 703 704 /// Create MipsTargetLowering objects. 705 const MipsTargetLowering * 706 createMips16TargetLowering(const MipsTargetMachine &TM, 707 const MipsSubtarget &STI); 708 const MipsTargetLowering * 709 createMipsSETargetLowering(const MipsTargetMachine &TM, 710 const MipsSubtarget &STI); 711 712 namespace Mips { 713 714 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 715 const TargetLibraryInfo *libInfo); 716 717 } // end namespace Mips 718 719 } // end namespace llvm 720 721 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 722