1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Google, Inc
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <fdtdec.h>
10 #include <pch.h>
11 #include <pci.h>
12 #include <asm/cpu.h>
13 #include <asm/gpio.h>
14 #include <asm/io.h>
15 #include <asm/pci.h>
16 #include <asm/arch/gpio.h>
17 #include <dt-bindings/gpio/x86-gpio.h>
18 #include <dm/pinctrl.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 enum {
23 MAX_GPIOS = 95,
24 };
25
26 #define PIRQ_SHIFT 16
27 #define CONF_MASK 0xffff
28
29 struct pin_info {
30 int node;
31 int phandle;
32 bool mode_gpio;
33 bool dir_input;
34 bool invert;
35 bool trigger_level;
36 bool output_high;
37 bool sense_disable;
38 bool owner_gpio;
39 bool route_smi;
40 bool irq_enable;
41 bool reset_rsmrst;
42 bool pirq_apic_route;
43 };
44
broadwell_pinctrl_read_configs(struct udevice * dev,struct pin_info * conf,int max_pins)45 static int broadwell_pinctrl_read_configs(struct udevice *dev,
46 struct pin_info *conf, int max_pins)
47 {
48 const void *blob = gd->fdt_blob;
49 int count = 0;
50 int node;
51
52 debug("%s: starting\n", __func__);
53 for (node = fdt_first_subnode(blob, dev_of_offset(dev));
54 node > 0;
55 node = fdt_next_subnode(blob, node)) {
56 int phandle = fdt_get_phandle(blob, node);
57
58 if (!phandle)
59 continue;
60 if (count == max_pins)
61 return -ENOSPC;
62
63 /* We've found a new configuration */
64 memset(conf, '\0', sizeof(*conf));
65 conf->node = node;
66 conf->phandle = phandle;
67 conf->mode_gpio = fdtdec_get_bool(blob, node, "mode-gpio");
68 if (fdtdec_get_int(blob, node, "direction", -1) == PIN_INPUT)
69 conf->dir_input = true;
70 conf->invert = fdtdec_get_bool(blob, node, "invert");
71 if (fdtdec_get_int(blob, node, "trigger", -1) == TRIGGER_LEVEL)
72 conf->trigger_level = true;
73 if (fdtdec_get_int(blob, node, "output-value", -1) == 1)
74 conf->output_high = true;
75 conf->sense_disable = fdtdec_get_bool(blob, node,
76 "sense-disable");
77 if (fdtdec_get_int(blob, node, "owner", -1) == OWNER_GPIO)
78 conf->owner_gpio = true;
79 if (fdtdec_get_int(blob, node, "route", -1) == ROUTE_SMI)
80 conf->route_smi = true;
81 conf->irq_enable = fdtdec_get_bool(blob, node, "irq-enable");
82 conf->reset_rsmrst = fdtdec_get_bool(blob, node,
83 "reset-rsmrst");
84 if (fdtdec_get_int(blob, node, "pirq-apic", -1) ==
85 PIRQ_APIC_ROUTE)
86 conf->pirq_apic_route = true;
87 debug("config: phandle=%d\n", phandle);
88 count++;
89 conf++;
90 }
91 debug("%s: Found %d configurations\n", __func__, count);
92
93 return count;
94 }
95
broadwell_pinctrl_lookup_phandle(struct pin_info * conf,int conf_count,int phandle)96 static int broadwell_pinctrl_lookup_phandle(struct pin_info *conf,
97 int conf_count, int phandle)
98 {
99 int i;
100
101 for (i = 0; i < conf_count; i++) {
102 if (conf[i].phandle == phandle)
103 return i;
104 }
105
106 return -ENOENT;
107 }
108
broadwell_pinctrl_read_pins(struct udevice * dev,struct pin_info * conf,int conf_count,int gpio_conf[],int num_gpios)109 static int broadwell_pinctrl_read_pins(struct udevice *dev,
110 struct pin_info *conf, int conf_count, int gpio_conf[],
111 int num_gpios)
112 {
113 const void *blob = gd->fdt_blob;
114 int count = 0;
115 int node;
116
117 for (node = fdt_first_subnode(blob, dev_of_offset(dev));
118 node > 0;
119 node = fdt_next_subnode(blob, node)) {
120 int len, i;
121 const u32 *prop = fdt_getprop(blob, node, "config", &len);
122
123 if (!prop)
124 continue;
125
126 /* There are three cells per pin */
127 count = len / (sizeof(u32) * 3);
128 debug("Found %d GPIOs to configure\n", count);
129 for (i = 0; i < count; i++) {
130 uint gpio = fdt32_to_cpu(prop[i * 3]);
131 uint phandle = fdt32_to_cpu(prop[i * 3 + 1]);
132 int val;
133
134 if (gpio >= num_gpios) {
135 debug("%s: GPIO %d out of range\n", __func__,
136 gpio);
137 return -EDOM;
138 }
139 val = broadwell_pinctrl_lookup_phandle(conf, conf_count,
140 phandle);
141 if (val < 0) {
142 debug("%s: Cannot find phandle %d\n", __func__,
143 phandle);
144 return -EINVAL;
145 }
146 gpio_conf[gpio] = val |
147 fdt32_to_cpu(prop[i * 3 + 2]) << PIRQ_SHIFT;
148 }
149 }
150
151 return 0;
152 }
153
broadwell_pinctrl_commit(struct pch_lp_gpio_regs * regs,struct pin_info * pin_info,int gpio_conf[],int count)154 static void broadwell_pinctrl_commit(struct pch_lp_gpio_regs *regs,
155 struct pin_info *pin_info,
156 int gpio_conf[], int count)
157 {
158 u32 owner_gpio[GPIO_BANKS] = {0};
159 u32 route_smi[GPIO_BANKS] = {0};
160 u32 irq_enable[GPIO_BANKS] = {0};
161 u32 reset_rsmrst[GPIO_BANKS] = {0};
162 u32 pirq2apic = 0;
163 int set, bit, gpio = 0;
164
165 for (gpio = 0; gpio < MAX_GPIOS; gpio++) {
166 int confnum = gpio_conf[gpio] & CONF_MASK;
167 struct pin_info *pin = &pin_info[confnum];
168 u32 val;
169
170 val = pin->mode_gpio << CONFA_MODE_SHIFT |
171 pin->dir_input << CONFA_DIR_SHIFT |
172 pin->invert << CONFA_INVERT_SHIFT |
173 pin->trigger_level << CONFA_TRIGGER_SHIFT |
174 pin->output_high << CONFA_OUTPUT_SHIFT;
175 outl(val, ®s->config[gpio].conf_a);
176 outl(pin->sense_disable << CONFB_SENSE_SHIFT,
177 ®s->config[gpio].conf_b);
178
179 /* Determine set and bit based on GPIO number */
180 set = gpio / GPIO_PER_BANK;
181 bit = gpio % GPIO_PER_BANK;
182
183 /* Apply settings to set specific bits */
184 owner_gpio[set] |= pin->owner_gpio << bit;
185 route_smi[set] |= pin->route_smi << bit;
186 irq_enable[set] |= pin->irq_enable << bit;
187 reset_rsmrst[set] |= pin->reset_rsmrst << bit;
188
189 /* PIRQ to IO-APIC map */
190 if (pin->pirq_apic_route)
191 pirq2apic |= gpio_conf[gpio] >> PIRQ_SHIFT;
192 debug("gpio %d: conf %d, mode_gpio %d, dir_input %d, output_high %d\n",
193 gpio, confnum, pin->mode_gpio, pin->dir_input,
194 pin->output_high);
195 }
196
197 for (set = 0; set < GPIO_BANKS; set++) {
198 outl(owner_gpio[set], ®s->own[set]);
199 outl(route_smi[set], ®s->gpi_route[set]);
200 outl(irq_enable[set], ®s->gpi_ie[set]);
201 outl(reset_rsmrst[set], ®s->rst_sel[set]);
202 }
203
204 outl(pirq2apic, ®s->pirq_to_ioxapic);
205 }
206
broadwell_pinctrl_probe(struct udevice * dev)207 static int broadwell_pinctrl_probe(struct udevice *dev)
208 {
209 struct pch_lp_gpio_regs *regs;
210 struct pin_info conf[12];
211 int gpio_conf[MAX_GPIOS];
212 struct udevice *pch;
213 int conf_count;
214 u32 gpiobase;
215 int ret;
216
217 ret = uclass_first_device(UCLASS_PCH, &pch);
218 if (ret)
219 return ret;
220 if (!pch)
221 return -ENODEV;
222 debug("%s: start\n", __func__);
223
224 /* Only init once, before relocation */
225 if (gd->flags & GD_FLG_RELOC)
226 return 0;
227
228 /*
229 * Get the memory/io base address to configure every pins.
230 * IOBASE is used to configure the mode/pads
231 * GPIOBASE is used to configure the direction and default value
232 */
233 ret = pch_get_gpio_base(pch, &gpiobase);
234 if (ret) {
235 debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
236 gpiobase);
237 return -EINVAL;
238 }
239
240 conf_count = broadwell_pinctrl_read_configs(dev, conf,
241 ARRAY_SIZE(conf));
242 if (conf_count < 0) {
243 debug("%s: Cannot read configs: err=%d\n", __func__, ret);
244 return conf_count;
245 }
246
247 /*
248 * Assume that pin settings are provided for every pin. Pins not
249 * mentioned will get the first config mentioned in the list.
250 */
251 ret = broadwell_pinctrl_read_pins(dev, conf, conf_count, gpio_conf,
252 MAX_GPIOS);
253 if (ret) {
254 debug("%s: Cannot read pin settings: err=%d\n", __func__, ret);
255 return ret;
256 }
257
258 regs = (struct pch_lp_gpio_regs *)gpiobase;
259 broadwell_pinctrl_commit(regs, conf, gpio_conf, ARRAY_SIZE(conf));
260
261 debug("%s: done\n", __func__);
262
263 return 0;
264 }
265
266 static const struct udevice_id broadwell_pinctrl_match[] = {
267 { .compatible = "intel,x86-broadwell-pinctrl",
268 .data = X86_SYSCON_PINCONF },
269 { /* sentinel */ }
270 };
271
272 U_BOOT_DRIVER(broadwell_pinctrl) = {
273 .name = "broadwell_pinctrl",
274 .id = UCLASS_SYSCON,
275 .of_match = broadwell_pinctrl_match,
276 .probe = broadwell_pinctrl_probe,
277 };
278