1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2008,2010 Freescale Semiconductor, Inc
4 * Andy Fleming
5 *
6 * Based (loosely) on the Linux code
7 */
8
9 #ifndef _MMC_H_
10 #define _MMC_H_
11
12 #include <linux/list.h>
13 #include <linux/sizes.h>
14 #include <linux/compiler.h>
15 #include <part.h>
16
17 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
18 #define MMC_SUPPORTS_TUNING
19 #endif
20 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
21 #define MMC_SUPPORTS_TUNING
22 #endif
23
24 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
25 #define SD_VERSION_SD (1U << 31)
26 #define MMC_VERSION_MMC (1U << 30)
27
28 #define MAKE_SDMMC_VERSION(a, b, c) \
29 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
30 #define MAKE_SD_VERSION(a, b, c) \
31 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
32 #define MAKE_MMC_VERSION(a, b, c) \
33 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
34
35 #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
36 (((u32)(x) >> 16) & 0xff)
37 #define EXTRACT_SDMMC_MINOR_VERSION(x) \
38 (((u32)(x) >> 8) & 0xff)
39 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
40 ((u32)(x) & 0xff)
41
42 #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
43 #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
44 #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
45 #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
46
47 #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
48 #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
49 #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
50 #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
51 #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
52 #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
53 #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
54 #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
55 #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
56 #define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
57 #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
58 #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
59 #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
60 #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
61
62 #define MMC_CAP(mode) (1 << mode)
63 #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
64 #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
65 #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
66 #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
67
68 #define MMC_MODE_8BIT BIT(30)
69 #define MMC_MODE_4BIT BIT(29)
70 #define MMC_MODE_1BIT BIT(28)
71 #define MMC_MODE_SPI BIT(27)
72
73
74 #define SD_DATA_4BIT 0x00040000
75
76 #define IS_SD(x) ((x)->version & SD_VERSION_SD)
77 #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
78
79 #define MMC_DATA_READ 1
80 #define MMC_DATA_WRITE 2
81
82 #define MMC_CMD_GO_IDLE_STATE 0
83 #define MMC_CMD_SEND_OP_COND 1
84 #define MMC_CMD_ALL_SEND_CID 2
85 #define MMC_CMD_SET_RELATIVE_ADDR 3
86 #define MMC_CMD_SET_DSR 4
87 #define MMC_CMD_SWITCH 6
88 #define MMC_CMD_SELECT_CARD 7
89 #define MMC_CMD_SEND_EXT_CSD 8
90 #define MMC_CMD_SEND_CSD 9
91 #define MMC_CMD_SEND_CID 10
92 #define MMC_CMD_STOP_TRANSMISSION 12
93 #define MMC_CMD_SEND_STATUS 13
94 #define MMC_CMD_SET_BLOCKLEN 16
95 #define MMC_CMD_READ_SINGLE_BLOCK 17
96 #define MMC_CMD_READ_MULTIPLE_BLOCK 18
97 #define MMC_CMD_SEND_TUNING_BLOCK 19
98 #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
99 #define MMC_CMD_SET_BLOCK_COUNT 23
100 #define MMC_CMD_WRITE_SINGLE_BLOCK 24
101 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
102 #define MMC_CMD_ERASE_GROUP_START 35
103 #define MMC_CMD_ERASE_GROUP_END 36
104 #define MMC_CMD_ERASE 38
105 #define MMC_CMD_APP_CMD 55
106 #define MMC_CMD_SPI_READ_OCR 58
107 #define MMC_CMD_SPI_CRC_ON_OFF 59
108 #define MMC_CMD_RES_MAN 62
109
110 #define MMC_CMD62_ARG1 0xefac62ec
111 #define MMC_CMD62_ARG2 0xcbaea7
112
113
114 #define SD_CMD_SEND_RELATIVE_ADDR 3
115 #define SD_CMD_SWITCH_FUNC 6
116 #define SD_CMD_SEND_IF_COND 8
117 #define SD_CMD_SWITCH_UHS18V 11
118
119 #define SD_CMD_APP_SET_BUS_WIDTH 6
120 #define SD_CMD_APP_SD_STATUS 13
121 #define SD_CMD_ERASE_WR_BLK_START 32
122 #define SD_CMD_ERASE_WR_BLK_END 33
123 #define SD_CMD_APP_SEND_OP_COND 41
124 #define SD_CMD_APP_SEND_SCR 51
125
mmc_is_tuning_cmd(uint cmdidx)126 static inline bool mmc_is_tuning_cmd(uint cmdidx)
127 {
128 if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
129 (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
130 return true;
131 return false;
132 }
133
134 /* SCR definitions in different words */
135 #define SD_HIGHSPEED_BUSY 0x00020000
136 #define SD_HIGHSPEED_SUPPORTED 0x00020000
137
138 #define UHS_SDR12_BUS_SPEED 0
139 #define HIGH_SPEED_BUS_SPEED 1
140 #define UHS_SDR25_BUS_SPEED 1
141 #define UHS_SDR50_BUS_SPEED 2
142 #define UHS_SDR104_BUS_SPEED 3
143 #define UHS_DDR50_BUS_SPEED 4
144
145 #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
146 #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
147 #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
148 #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
149 #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
150
151 #define OCR_BUSY 0x80000000
152 #define OCR_HCS 0x40000000
153 #define OCR_S18R 0x1000000
154 #define OCR_VOLTAGE_MASK 0x007FFF80
155 #define OCR_ACCESS_MODE 0x60000000
156
157 #define MMC_ERASE_ARG 0x00000000
158 #define MMC_SECURE_ERASE_ARG 0x80000000
159 #define MMC_TRIM_ARG 0x00000001
160 #define MMC_DISCARD_ARG 0x00000003
161 #define MMC_SECURE_TRIM1_ARG 0x80000001
162 #define MMC_SECURE_TRIM2_ARG 0x80008000
163
164 #define MMC_STATUS_MASK (~0x0206BF7F)
165 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
166 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
167 #define MMC_STATUS_CURR_STATE (0xf << 9)
168 #define MMC_STATUS_ERROR (1 << 19)
169
170 #define MMC_STATE_PRG (7 << 9)
171
172 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
173 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
174 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
175 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
176 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
177 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
178 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
179 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
180 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
181 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
182 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
183 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
184 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
185 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
186 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
187 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
188 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
189
190 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
191 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
192 addressed by index which are
193 1 in value field */
194 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
195 addressed by index, which are
196 1 in value field */
197 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
198
199 #define SD_SWITCH_CHECK 0
200 #define SD_SWITCH_SWITCH 1
201
202 /*
203 * EXT_CSD fields
204 */
205 #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
206 #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
207 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
208 #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
209 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
210 #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
211 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
212 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
213 #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
214 #define EXT_CSD_WR_REL_PARAM 166 /* R */
215 #define EXT_CSD_WR_REL_SET 167 /* R/W */
216 #define EXT_CSD_RPMB_MULT 168 /* RO */
217 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
218 #define EXT_CSD_BOOT_BUS_WIDTH 177
219 #define EXT_CSD_PART_CONF 179 /* R/W */
220 #define EXT_CSD_BUS_WIDTH 183 /* R/W */
221 #define EXT_CSD_HS_TIMING 185 /* R/W */
222 #define EXT_CSD_REV 192 /* RO */
223 #define EXT_CSD_CARD_TYPE 196 /* RO */
224 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
225 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
226 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
227 #define EXT_CSD_BOOT_MULT 226 /* RO */
228 #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
229
230 /*
231 * EXT_CSD field definitions
232 */
233
234 #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
235 #define EXT_CSD_CMD_SET_SECURE (1 << 1)
236 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
237
238 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
239 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
240 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
241 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
242 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
243 | EXT_CSD_CARD_TYPE_DDR_1_2V)
244
245 #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
246 /* SDR mode @1.8V I/O */
247 #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
248 /* SDR mode @1.2V I/O */
249 #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
250 EXT_CSD_CARD_TYPE_HS200_1_2V)
251
252 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
253 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
254 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
255 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
256 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
257 #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
258
259 #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
260 #define EXT_CSD_TIMING_HS 1 /* HS */
261 #define EXT_CSD_TIMING_HS200 2 /* HS200 */
262
263 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
264 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
265 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
266 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
267
268 #define EXT_CSD_BOOT_ACK(x) (x << 6)
269 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
270 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
271
272 #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
273 #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
274 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
275
276 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
277 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
278 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
279
280 #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
281
282 #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
283 #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
284
285 #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
286
287 #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
288 #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
289
290 #define R1_ILLEGAL_COMMAND (1 << 22)
291 #define R1_APP_CMD (1 << 5)
292
293 #define MMC_RSP_PRESENT (1 << 0)
294 #define MMC_RSP_136 (1 << 1) /* 136 bit response */
295 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
296 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
297 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
298
299 #define MMC_RSP_NONE (0)
300 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
301 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
302 MMC_RSP_BUSY)
303 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
304 #define MMC_RSP_R3 (MMC_RSP_PRESENT)
305 #define MMC_RSP_R4 (MMC_RSP_PRESENT)
306 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
307 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
308 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
309
310 #define MMCPART_NOAVAILABLE (0xff)
311 #define PART_ACCESS_MASK (0x7)
312 #define PART_SUPPORT (0x1)
313 #define ENHNCD_SUPPORT (0x2)
314 #define PART_ENH_ATTRIB (0x1f)
315
316 #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
317 #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
318
319 enum mmc_voltage {
320 MMC_SIGNAL_VOLTAGE_000 = 0,
321 MMC_SIGNAL_VOLTAGE_120 = 1,
322 MMC_SIGNAL_VOLTAGE_180 = 2,
323 MMC_SIGNAL_VOLTAGE_330 = 4,
324 };
325
326 #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
327 MMC_SIGNAL_VOLTAGE_180 |\
328 MMC_SIGNAL_VOLTAGE_330)
329
330 /* Maximum block size for MMC */
331 #define MMC_MAX_BLOCK_LEN 512
332
333 /* The number of MMC physical partitions. These consist of:
334 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
335 */
336 #define MMC_NUM_BOOT_PARTITION 2
337 #define MMC_PART_RPMB 3 /* RPMB partition number */
338
339 /* Driver model support */
340
341 /**
342 * struct mmc_uclass_priv - Holds information about a device used by the uclass
343 */
344 struct mmc_uclass_priv {
345 struct mmc *mmc;
346 };
347
348 /**
349 * mmc_get_mmc_dev() - get the MMC struct pointer for a device
350 *
351 * Provided that the device is already probed and ready for use, this value
352 * will be available.
353 *
354 * @dev: Device
355 * @return associated mmc struct pointer if available, else NULL
356 */
357 struct mmc *mmc_get_mmc_dev(struct udevice *dev);
358
359 /* End of driver model support */
360
361 struct mmc_cid {
362 unsigned long psn;
363 unsigned short oid;
364 unsigned char mid;
365 unsigned char prv;
366 unsigned char mdt;
367 char pnm[7];
368 };
369
370 struct mmc_cmd {
371 ushort cmdidx;
372 uint resp_type;
373 uint cmdarg;
374 uint response[4];
375 };
376
377 struct mmc_data {
378 union {
379 char *dest;
380 const char *src; /* src buffers don't get written to */
381 };
382 uint flags;
383 uint blocks;
384 uint blocksize;
385 };
386
387 /* forward decl. */
388 struct mmc;
389
390 #if CONFIG_IS_ENABLED(DM_MMC)
391 struct dm_mmc_ops {
392 /**
393 * send_cmd() - Send a command to the MMC device
394 *
395 * @dev: Device to receive the command
396 * @cmd: Command to send
397 * @data: Additional data to send/receive
398 * @return 0 if OK, -ve on error
399 */
400 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
401 struct mmc_data *data);
402
403 /**
404 * set_ios() - Set the I/O speed/width for an MMC device
405 *
406 * @dev: Device to update
407 * @return 0 if OK, -ve on error
408 */
409 int (*set_ios)(struct udevice *dev);
410
411 /**
412 * send_init_stream() - send the initialization stream: 74 clock cycles
413 * This is used after power up before sending the first command
414 *
415 * @dev: Device to update
416 */
417 void (*send_init_stream)(struct udevice *dev);
418
419 /**
420 * get_cd() - See whether a card is present
421 *
422 * @dev: Device to check
423 * @return 0 if not present, 1 if present, -ve on error
424 */
425 int (*get_cd)(struct udevice *dev);
426
427 /**
428 * get_wp() - See whether a card has write-protect enabled
429 *
430 * @dev: Device to check
431 * @return 0 if write-enabled, 1 if write-protected, -ve on error
432 */
433 int (*get_wp)(struct udevice *dev);
434
435 #ifdef MMC_SUPPORTS_TUNING
436 /**
437 * execute_tuning() - Start the tuning process
438 *
439 * @dev: Device to start the tuning
440 * @opcode: Command opcode to send
441 * @return 0 if OK, -ve on error
442 */
443 int (*execute_tuning)(struct udevice *dev, uint opcode);
444 #endif
445
446 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
447 /**
448 * wait_dat0() - wait until dat0 is in the target state
449 * (CLK must be running during the wait)
450 *
451 * @dev: Device to check
452 * @state: target state
453 * @timeout: timeout in us
454 * @return 0 if dat0 is in the target state, -ve on error
455 */
456 int (*wait_dat0)(struct udevice *dev, int state, int timeout);
457 #endif
458 };
459
460 #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
461
462 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
463 struct mmc_data *data);
464 int dm_mmc_set_ios(struct udevice *dev);
465 void dm_mmc_send_init_stream(struct udevice *dev);
466 int dm_mmc_get_cd(struct udevice *dev);
467 int dm_mmc_get_wp(struct udevice *dev);
468 int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
469 int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
470
471 /* Transition functions for compatibility */
472 int mmc_set_ios(struct mmc *mmc);
473 void mmc_send_init_stream(struct mmc *mmc);
474 int mmc_getcd(struct mmc *mmc);
475 int mmc_getwp(struct mmc *mmc);
476 int mmc_execute_tuning(struct mmc *mmc, uint opcode);
477 int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
478
479 #else
480 struct mmc_ops {
481 int (*send_cmd)(struct mmc *mmc,
482 struct mmc_cmd *cmd, struct mmc_data *data);
483 int (*set_ios)(struct mmc *mmc);
484 int (*init)(struct mmc *mmc);
485 int (*getcd)(struct mmc *mmc);
486 int (*getwp)(struct mmc *mmc);
487 };
488 #endif
489
490 struct mmc_config {
491 const char *name;
492 #if !CONFIG_IS_ENABLED(DM_MMC)
493 const struct mmc_ops *ops;
494 #endif
495 uint host_caps;
496 uint voltages;
497 uint f_min;
498 uint f_max;
499 uint b_max;
500 unsigned char part_type;
501 };
502
503 struct sd_ssr {
504 unsigned int au; /* In sectors */
505 unsigned int erase_timeout; /* In milliseconds */
506 unsigned int erase_offset; /* In milliseconds */
507 };
508
509 enum bus_mode {
510 MMC_LEGACY,
511 SD_LEGACY,
512 MMC_HS,
513 SD_HS,
514 MMC_HS_52,
515 MMC_DDR_52,
516 UHS_SDR12,
517 UHS_SDR25,
518 UHS_SDR50,
519 UHS_DDR50,
520 UHS_SDR104,
521 MMC_HS_200,
522 MMC_MODES_END
523 };
524
525 const char *mmc_mode_name(enum bus_mode mode);
526 void mmc_dump_capabilities(const char *text, uint caps);
527
mmc_is_mode_ddr(enum bus_mode mode)528 static inline bool mmc_is_mode_ddr(enum bus_mode mode)
529 {
530 if (mode == MMC_DDR_52)
531 return true;
532 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
533 else if (mode == UHS_DDR50)
534 return true;
535 #endif
536 else
537 return false;
538 }
539
540 #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
541 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
542 MMC_CAP(UHS_DDR50))
543
supports_uhs(uint caps)544 static inline bool supports_uhs(uint caps)
545 {
546 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
547 return (caps & UHS_CAPS) ? true : false;
548 #else
549 return false;
550 #endif
551 }
552
553 /*
554 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
555 * with mmc_get_mmc_dev().
556 *
557 * TODO struct mmc should be in mmc_private but it's hard to fix right now
558 */
559 struct mmc {
560 #if !CONFIG_IS_ENABLED(BLK)
561 struct list_head link;
562 #endif
563 const struct mmc_config *cfg; /* provided configuration */
564 uint version;
565 void *priv;
566 uint has_init;
567 int high_capacity;
568 bool clk_disable; /* true if the clock can be turned off */
569 uint bus_width;
570 uint clock;
571 enum mmc_voltage signal_voltage;
572 uint card_caps;
573 uint host_caps;
574 uint ocr;
575 uint dsr;
576 uint dsr_imp;
577 uint scr[2];
578 uint csd[4];
579 uint cid[4];
580 ushort rca;
581 u8 part_support;
582 u8 part_attr;
583 u8 wr_rel_set;
584 u8 part_config;
585 uint tran_speed;
586 uint legacy_speed; /* speed for the legacy mode provided by the card */
587 uint read_bl_len;
588 #if CONFIG_IS_ENABLED(MMC_WRITE)
589 uint write_bl_len;
590 uint erase_grp_size; /* in 512-byte sectors */
591 #endif
592 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
593 uint hc_wp_grp_size; /* in 512-byte sectors */
594 #endif
595 #if CONFIG_IS_ENABLED(MMC_WRITE)
596 struct sd_ssr ssr; /* SD status register */
597 #endif
598 u64 capacity;
599 u64 capacity_user;
600 u64 capacity_boot;
601 u64 capacity_rpmb;
602 u64 capacity_gp[4];
603 #ifndef CONFIG_SPL_BUILD
604 u64 enh_user_start;
605 u64 enh_user_size;
606 #endif
607 #if !CONFIG_IS_ENABLED(BLK)
608 struct blk_desc block_dev;
609 #endif
610 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
611 char init_in_progress; /* 1 if we have done mmc_start_init() */
612 char preinit; /* start init as early as possible */
613 int ddr_mode;
614 #if CONFIG_IS_ENABLED(DM_MMC)
615 struct udevice *dev; /* Device for this MMC controller */
616 #if CONFIG_IS_ENABLED(DM_REGULATOR)
617 struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
618 struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
619 #endif
620 #endif
621 u8 *ext_csd;
622 u32 cardtype; /* cardtype read from the MMC */
623 enum mmc_voltage current_voltage;
624 enum bus_mode selected_mode; /* mode currently used */
625 enum bus_mode best_mode; /* best mode is the supported mode with the
626 * highest bandwidth. It may not always be the
627 * operating mode due to limitations when
628 * accessing the boot partitions
629 */
630 u32 quirks;
631 };
632
633 struct mmc_hwpart_conf {
634 struct {
635 uint enh_start; /* in 512-byte sectors */
636 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
637 unsigned wr_rel_change : 1;
638 unsigned wr_rel_set : 1;
639 } user;
640 struct {
641 uint size; /* in 512-byte sectors */
642 unsigned enhanced : 1;
643 unsigned wr_rel_change : 1;
644 unsigned wr_rel_set : 1;
645 } gp_part[4];
646 };
647
648 enum mmc_hwpart_conf_mode {
649 MMC_HWPART_CONF_CHECK,
650 MMC_HWPART_CONF_SET,
651 MMC_HWPART_CONF_COMPLETE,
652 };
653
654 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
655
656 /**
657 * mmc_bind() - Set up a new MMC device ready for probing
658 *
659 * A child block device is bound with the IF_TYPE_MMC interface type. This
660 * allows the device to be used with CONFIG_BLK
661 *
662 * @dev: MMC device to set up
663 * @mmc: MMC struct
664 * @cfg: MMC configuration
665 * @return 0 if OK, -ve on error
666 */
667 int mmc_bind(struct udevice *dev, struct mmc *mmc,
668 const struct mmc_config *cfg);
669 void mmc_destroy(struct mmc *mmc);
670
671 /**
672 * mmc_unbind() - Unbind a MMC device's child block device
673 *
674 * @dev: MMC device
675 * @return 0 if OK, -ve on error
676 */
677 int mmc_unbind(struct udevice *dev);
678 int mmc_initialize(bd_t *bis);
679 int mmc_init(struct mmc *mmc);
680 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
681
682 /**
683 * mmc_of_parse() - Parse the device tree to get the capabilities of the host
684 *
685 * @dev: MMC device
686 * @cfg: MMC configuration
687 * @return 0 if OK, -ve on error
688 */
689 int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
690
691 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
692
693 /**
694 * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
695 *
696 * @voltage: The mmc_voltage to convert
697 * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
698 */
699 int mmc_voltage_to_mv(enum mmc_voltage voltage);
700
701 /**
702 * mmc_set_clock() - change the bus clock
703 * @mmc: MMC struct
704 * @clock: bus frequency in Hz
705 * @disable: flag indicating if the clock must on or off
706 * @return 0 if OK, -ve on error
707 */
708 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
709
710 #define MMC_CLK_ENABLE false
711 #define MMC_CLK_DISABLE true
712
713 struct mmc *find_mmc_device(int dev_num);
714 int mmc_set_dev(int dev_num);
715 void print_mmc_devices(char separator);
716
717 /**
718 * get_mmc_num() - get the total MMC device number
719 *
720 * @return 0 if there is no MMC device, else the number of devices
721 */
722 int get_mmc_num(void);
723 int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
724 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
725 enum mmc_hwpart_conf_mode mode);
726
727 #if !CONFIG_IS_ENABLED(DM_MMC)
728 int mmc_getcd(struct mmc *mmc);
729 int board_mmc_getcd(struct mmc *mmc);
730 int mmc_getwp(struct mmc *mmc);
731 int board_mmc_getwp(struct mmc *mmc);
732 #endif
733
734 int mmc_set_dsr(struct mmc *mmc, u16 val);
735 /* Function to change the size of boot partition and rpmb partitions */
736 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
737 unsigned long rpmbsize);
738 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
739 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
740 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
741 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
742 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
743 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
744 /* Functions to read / write the RPMB partition */
745 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
746 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
747 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
748 unsigned short cnt, unsigned char *key);
749 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
750 unsigned short cnt, unsigned char *key);
751 #ifdef CONFIG_CMD_BKOPS_ENABLE
752 int mmc_set_bkops_enable(struct mmc *mmc);
753 #endif
754
755 /**
756 * Start device initialization and return immediately; it does not block on
757 * polling OCR (operation condition register) status. Then you should call
758 * mmc_init, which would block on polling OCR status and complete the device
759 * initializatin.
760 *
761 * @param mmc Pointer to a MMC device struct
762 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
763 */
764 int mmc_start_init(struct mmc *mmc);
765
766 /**
767 * Set preinit flag of mmc device.
768 *
769 * This will cause the device to be pre-inited during mmc_initialize(),
770 * which may save boot time if the device is not accessed until later.
771 * Some eMMC devices take 200-300ms to init, but unfortunately they
772 * must be sent a series of commands to even get them to start preparing
773 * for operation.
774 *
775 * @param mmc Pointer to a MMC device struct
776 * @param preinit preinit flag value
777 */
778 void mmc_set_preinit(struct mmc *mmc, int preinit);
779
780 #ifdef CONFIG_MMC_SPI
781 #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
782 #else
783 #define mmc_host_is_spi(mmc) 0
784 #endif
785 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
786
787 void board_mmc_power_init(void);
788 int board_mmc_init(bd_t *bis);
789 int cpu_mmc_init(bd_t *bis);
790 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
791 int mmc_get_env_dev(void);
792
793 /* Set block count limit because of 16 bit register limit on some hardware*/
794 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
795 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
796 #endif
797
798 /**
799 * mmc_get_blk_desc() - Get the block descriptor for an MMC device
800 *
801 * @mmc: MMC device
802 * @return block device if found, else NULL
803 */
804 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
805
806 #endif /* _MMC_H_ */
807