1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the ARM target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16
17 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
18 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
19
20 #include "ARMMCTargetDesc.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "Utils/ARMBaseInfo.h"
23
24 namespace llvm {
25
26 namespace ARM_PROC {
27 enum IMod {
28 IE = 2,
29 ID = 3
30 };
31
32 enum IFlags {
33 F = 1,
34 I = 2,
35 A = 4
36 };
37
IFlagsToString(unsigned val)38 inline static const char *IFlagsToString(unsigned val) {
39 switch (val) {
40 default: llvm_unreachable("Unknown iflags operand");
41 case F: return "f";
42 case I: return "i";
43 case A: return "a";
44 }
45 }
46
IModToString(unsigned val)47 inline static const char *IModToString(unsigned val) {
48 switch (val) {
49 default: llvm_unreachable("Unknown imod operand");
50 case IE: return "ie";
51 case ID: return "id";
52 }
53 }
54 }
55
56 namespace ARM_MB {
57 // The Memory Barrier Option constants map directly to the 4-bit encoding of
58 // the option field for memory barrier operations.
59 enum MemBOpt {
60 RESERVED_0 = 0,
61 OSHLD = 1,
62 OSHST = 2,
63 OSH = 3,
64 RESERVED_4 = 4,
65 NSHLD = 5,
66 NSHST = 6,
67 NSH = 7,
68 RESERVED_8 = 8,
69 ISHLD = 9,
70 ISHST = 10,
71 ISH = 11,
72 RESERVED_12 = 12,
73 LD = 13,
74 ST = 14,
75 SY = 15
76 };
77
MemBOptToString(unsigned val,bool HasV8)78 inline static const char *MemBOptToString(unsigned val, bool HasV8) {
79 switch (val) {
80 default: llvm_unreachable("Unknown memory operation");
81 case SY: return "sy";
82 case ST: return "st";
83 case LD: return HasV8 ? "ld" : "#0xd";
84 case RESERVED_12: return "#0xc";
85 case ISH: return "ish";
86 case ISHST: return "ishst";
87 case ISHLD: return HasV8 ? "ishld" : "#0x9";
88 case RESERVED_8: return "#0x8";
89 case NSH: return "nsh";
90 case NSHST: return "nshst";
91 case NSHLD: return HasV8 ? "nshld" : "#0x5";
92 case RESERVED_4: return "#0x4";
93 case OSH: return "osh";
94 case OSHST: return "oshst";
95 case OSHLD: return HasV8 ? "oshld" : "#0x1";
96 case RESERVED_0: return "#0x0";
97 }
98 }
99 } // namespace ARM_MB
100
101 namespace ARM_TSB {
102 enum TraceSyncBOpt {
103 CSYNC = 0
104 };
105
TraceSyncBOptToString(unsigned val)106 inline static const char *TraceSyncBOptToString(unsigned val) {
107 switch (val) {
108 default:
109 llvm_unreachable("Unknown trace synchronization barrier operation");
110 case CSYNC: return "csync";
111 }
112 }
113 } // namespace ARM_TSB
114
115 namespace ARM_ISB {
116 enum InstSyncBOpt {
117 RESERVED_0 = 0,
118 RESERVED_1 = 1,
119 RESERVED_2 = 2,
120 RESERVED_3 = 3,
121 RESERVED_4 = 4,
122 RESERVED_5 = 5,
123 RESERVED_6 = 6,
124 RESERVED_7 = 7,
125 RESERVED_8 = 8,
126 RESERVED_9 = 9,
127 RESERVED_10 = 10,
128 RESERVED_11 = 11,
129 RESERVED_12 = 12,
130 RESERVED_13 = 13,
131 RESERVED_14 = 14,
132 SY = 15
133 };
134
InstSyncBOptToString(unsigned val)135 inline static const char *InstSyncBOptToString(unsigned val) {
136 switch (val) {
137 default:
138 llvm_unreachable("Unknown memory operation");
139 case RESERVED_0: return "#0x0";
140 case RESERVED_1: return "#0x1";
141 case RESERVED_2: return "#0x2";
142 case RESERVED_3: return "#0x3";
143 case RESERVED_4: return "#0x4";
144 case RESERVED_5: return "#0x5";
145 case RESERVED_6: return "#0x6";
146 case RESERVED_7: return "#0x7";
147 case RESERVED_8: return "#0x8";
148 case RESERVED_9: return "#0x9";
149 case RESERVED_10: return "#0xa";
150 case RESERVED_11: return "#0xb";
151 case RESERVED_12: return "#0xc";
152 case RESERVED_13: return "#0xd";
153 case RESERVED_14: return "#0xe";
154 case SY: return "sy";
155 }
156 }
157 } // namespace ARM_ISB
158
159 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
160 ///
isARMLowRegister(unsigned Reg)161 static inline bool isARMLowRegister(unsigned Reg) {
162 using namespace ARM;
163 switch (Reg) {
164 case R0: case R1: case R2: case R3:
165 case R4: case R5: case R6: case R7:
166 return true;
167 default:
168 return false;
169 }
170 }
171
172 /// ARMII - This namespace holds all of the target specific flags that
173 /// instruction info tracks.
174 ///
175 namespace ARMII {
176
177 /// ARM Index Modes
178 enum IndexMode {
179 IndexModeNone = 0,
180 IndexModePre = 1,
181 IndexModePost = 2,
182 IndexModeUpd = 3
183 };
184
185 /// ARM Addressing Modes
186 enum AddrMode {
187 AddrModeNone = 0,
188 AddrMode1 = 1,
189 AddrMode2 = 2,
190 AddrMode3 = 3,
191 AddrMode4 = 4,
192 AddrMode5 = 5,
193 AddrMode6 = 6,
194 AddrModeT1_1 = 7,
195 AddrModeT1_2 = 8,
196 AddrModeT1_4 = 9,
197 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
198 AddrModeT2_i12 = 11,
199 AddrModeT2_i8 = 12,
200 AddrModeT2_so = 13,
201 AddrModeT2_pc = 14, // +/- i12 for pc relative data
202 AddrModeT2_i8s4 = 15, // i8 * 4
203 AddrMode_i12 = 16,
204 AddrMode5FP16 = 17, // i8 * 2
205 AddrModeT2_ldrex = 18, // i8 * 4, with unscaled offset in MCInst
206 };
207
AddrModeToString(AddrMode addrmode)208 inline static const char *AddrModeToString(AddrMode addrmode) {
209 switch (addrmode) {
210 case AddrModeNone: return "AddrModeNone";
211 case AddrMode1: return "AddrMode1";
212 case AddrMode2: return "AddrMode2";
213 case AddrMode3: return "AddrMode3";
214 case AddrMode4: return "AddrMode4";
215 case AddrMode5: return "AddrMode5";
216 case AddrMode5FP16: return "AddrMode5FP16";
217 case AddrMode6: return "AddrMode6";
218 case AddrModeT1_1: return "AddrModeT1_1";
219 case AddrModeT1_2: return "AddrModeT1_2";
220 case AddrModeT1_4: return "AddrModeT1_4";
221 case AddrModeT1_s: return "AddrModeT1_s";
222 case AddrModeT2_i12: return "AddrModeT2_i12";
223 case AddrModeT2_i8: return "AddrModeT2_i8";
224 case AddrModeT2_so: return "AddrModeT2_so";
225 case AddrModeT2_pc: return "AddrModeT2_pc";
226 case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
227 case AddrMode_i12: return "AddrMode_i12";
228 case AddrModeT2_ldrex:return "AddrModeT2_ldrex";
229 }
230 }
231
232 /// Target Operand Flag enum.
233 enum TOF {
234 //===------------------------------------------------------------------===//
235 // ARM Specific MachineOperand flags.
236
237 MO_NO_FLAG = 0,
238
239 /// MO_LO16 - On a symbol operand, this represents a relocation containing
240 /// lower 16 bit of the address. Used only via movw instruction.
241 MO_LO16 = 0x1,
242
243 /// MO_HI16 - On a symbol operand, this represents a relocation containing
244 /// higher 16 bit of the address. Used only via movt instruction.
245 MO_HI16 = 0x2,
246
247 /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
248 /// just that part of the flag set.
249 MO_OPTION_MASK = 0x3,
250
251 /// MO_GOT - On a symbol operand, this represents a GOT relative relocation.
252 MO_GOT = 0x8,
253
254 /// MO_SBREL - On a symbol operand, this represents a static base relative
255 /// relocation. Used in movw and movt instructions.
256 MO_SBREL = 0x10,
257
258 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
259 /// to the symbol is for an import stub. This is used for DLL import
260 /// storage class indication on Windows.
261 MO_DLLIMPORT = 0x20,
262
263 /// MO_SECREL - On a symbol operand this indicates that the immediate is
264 /// the offset from beginning of section.
265 ///
266 /// This is the TLS offset for the COFF/Windows TLS mechanism.
267 MO_SECREL = 0x40,
268
269 /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
270 /// represents a symbol which, if indirect, will get special Darwin mangling
271 /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
272 /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
273 /// example).
274 MO_NONLAZY = 0x80,
275
276 // It's undefined behaviour if an enum overflows the range between its
277 // smallest and largest values, but since these are |ed together, it can
278 // happen. Put a sentinel in (values of this enum are stored as "unsigned
279 // char").
280 MO_UNUSED_MAXIMUM = 0xff
281 };
282
283 enum {
284 //===------------------------------------------------------------------===//
285 // Instruction Flags.
286
287 //===------------------------------------------------------------------===//
288 // This four-bit field describes the addressing mode used.
289 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
290
291 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
292 // and store ops only. Generic "updating" flag is used for ld/st multiple.
293 // The index mode enums are declared in ARMBaseInfo.h
294 IndexModeShift = 5,
295 IndexModeMask = 3 << IndexModeShift,
296
297 //===------------------------------------------------------------------===//
298 // Instruction encoding formats.
299 //
300 FormShift = 7,
301 FormMask = 0x3f << FormShift,
302
303 // Pseudo instructions
304 Pseudo = 0 << FormShift,
305
306 // Multiply instructions
307 MulFrm = 1 << FormShift,
308
309 // Branch instructions
310 BrFrm = 2 << FormShift,
311 BrMiscFrm = 3 << FormShift,
312
313 // Data Processing instructions
314 DPFrm = 4 << FormShift,
315 DPSoRegFrm = 5 << FormShift,
316
317 // Load and Store
318 LdFrm = 6 << FormShift,
319 StFrm = 7 << FormShift,
320 LdMiscFrm = 8 << FormShift,
321 StMiscFrm = 9 << FormShift,
322 LdStMulFrm = 10 << FormShift,
323
324 LdStExFrm = 11 << FormShift,
325
326 // Miscellaneous arithmetic instructions
327 ArithMiscFrm = 12 << FormShift,
328 SatFrm = 13 << FormShift,
329
330 // Extend instructions
331 ExtFrm = 14 << FormShift,
332
333 // VFP formats
334 VFPUnaryFrm = 15 << FormShift,
335 VFPBinaryFrm = 16 << FormShift,
336 VFPConv1Frm = 17 << FormShift,
337 VFPConv2Frm = 18 << FormShift,
338 VFPConv3Frm = 19 << FormShift,
339 VFPConv4Frm = 20 << FormShift,
340 VFPConv5Frm = 21 << FormShift,
341 VFPLdStFrm = 22 << FormShift,
342 VFPLdStMulFrm = 23 << FormShift,
343 VFPMiscFrm = 24 << FormShift,
344
345 // Thumb format
346 ThumbFrm = 25 << FormShift,
347
348 // Miscelleaneous format
349 MiscFrm = 26 << FormShift,
350
351 // NEON formats
352 NGetLnFrm = 27 << FormShift,
353 NSetLnFrm = 28 << FormShift,
354 NDupFrm = 29 << FormShift,
355 NLdStFrm = 30 << FormShift,
356 N1RegModImmFrm= 31 << FormShift,
357 N2RegFrm = 32 << FormShift,
358 NVCVTFrm = 33 << FormShift,
359 NVDupLnFrm = 34 << FormShift,
360 N2RegVShLFrm = 35 << FormShift,
361 N2RegVShRFrm = 36 << FormShift,
362 N3RegFrm = 37 << FormShift,
363 N3RegVShFrm = 38 << FormShift,
364 NVExtFrm = 39 << FormShift,
365 NVMulSLFrm = 40 << FormShift,
366 NVTBLFrm = 41 << FormShift,
367 N3RegCplxFrm = 43 << FormShift,
368
369 //===------------------------------------------------------------------===//
370 // Misc flags.
371
372 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
373 // it doesn't have a Rn operand.
374 UnaryDP = 1 << 13,
375
376 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
377 // a 16-bit Thumb instruction if certain conditions are met.
378 Xform16Bit = 1 << 14,
379
380 // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
381 // instruction. Used by the parser to determine whether to require the 'S'
382 // suffix on the mnemonic (when not in an IT block) or preclude it (when
383 // in an IT block).
384 ThumbArithFlagSetting = 1 << 18,
385
386 //===------------------------------------------------------------------===//
387 // Code domain.
388 DomainShift = 15,
389 DomainMask = 7 << DomainShift,
390 DomainGeneral = 0 << DomainShift,
391 DomainVFP = 1 << DomainShift,
392 DomainNEON = 2 << DomainShift,
393 DomainNEONA8 = 4 << DomainShift,
394
395 //===------------------------------------------------------------------===//
396 // Field shifts - such shifts are used to set field while generating
397 // machine instructions.
398 //
399 // FIXME: This list will need adjusting/fixing as the MC code emitter
400 // takes shape and the ARMCodeEmitter.cpp bits go away.
401 ShiftTypeShift = 4,
402
403 M_BitShift = 5,
404 ShiftImmShift = 5,
405 ShiftShift = 7,
406 N_BitShift = 7,
407 ImmHiShift = 8,
408 SoRotImmShift = 8,
409 RegRsShift = 8,
410 ExtRotImmShift = 10,
411 RegRdLoShift = 12,
412 RegRdShift = 12,
413 RegRdHiShift = 16,
414 RegRnShift = 16,
415 S_BitShift = 20,
416 W_BitShift = 21,
417 AM3_I_BitShift = 22,
418 D_BitShift = 22,
419 U_BitShift = 23,
420 P_BitShift = 24,
421 I_BitShift = 25,
422 CondShift = 28
423 };
424
425 } // end namespace ARMII
426
427 } // end namespace llvm;
428
429 #endif
430