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Searched defs:OpIdx (Results 1 – 25 of 100) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp212 AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, in getLdStUImm12OpValue()
233 AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, in getAdrLabelOpValue()
259 AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, in getAddSubImmOpValue()
296 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in getCondBranchTargetOpValue()
317 AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, in getLoadLiteralOpValue()
337 AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, in getMemExtendOpValue()
346 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, in getMoveWideImmOpValue()
366 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in getTestBranchTargetOpValue()
387 AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getBranchTargetOpValue()
415 AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, in getVecShifterOpValue()
[all …]
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp197 AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, in getLdStUImm12OpValue()
218 AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, in getAdrLabelOpValue()
244 AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, in getAddSubImmOpValue()
272 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in getCondBranchTargetOpValue()
293 AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, in getLoadLiteralOpValue()
313 AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, in getMemExtendOpValue()
322 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, in getMoveWideImmOpValue()
342 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in getTestBranchTargetOpValue()
363 AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getBranchTargetOpValue()
391 AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, in getVecShifterOpValue()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h88 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
186 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
408 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
457 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
474 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
503 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
522 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
546 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
571 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
588 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp165 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, in getLdStmModeOpValue()
431 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, in EncodeAddrModeOpValues()
459 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getBranchTargetOpValue()
496 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBLTargetOpValue()
508 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBLXTargetOpValue()
519 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBRTargetOpValue()
530 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBCCTargetOpValue()
541 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbCBTargetOpValue()
569 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getBranchTargetOpValue()
582 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getARMBranchTargetOpValue()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp204 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, in getLdStmModeOpValue()
562 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, in EncodeAddrModeOpValues()
591 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getBranchTargetOpValue()
629 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBLTargetOpValue()
642 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBLXTargetOpValue()
654 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBRTargetOpValue()
666 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBCCTargetOpValue()
678 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbCBTargetOpValue()
707 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getBranchTargetOpValue()
721 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getARMBranchTargetOpValue()
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp191 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, in getLdStmModeOpValue()
551 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, in EncodeAddrModeOpValues()
580 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getBranchTargetOpValue()
618 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBLTargetOpValue()
631 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBLXTargetOpValue()
643 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBRTargetOpValue()
655 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbBCCTargetOpValue()
667 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, in getThumbCBTargetOpValue()
696 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getBranchTargetOpValue()
710 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getARMBranchTargetOpValue()
[all …]
/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp186 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, in getRegBankFromConstraints()
223 for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) { in getInstrMappingImpl() local
288 for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) { in getInstrMappingImpl() local
338 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx; in applyDefaultMapping() local
454 unsigned OpIdx, unsigned MaskSize, const RegisterBank &RegBank) { in setOperandMapping()
503 for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) { in print() local
525 RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) { in getVRegsMem()
561 void RegisterBankInfo::OperandsMapper::createVRegs(unsigned OpIdx) { in createVRegs()
577 void RegisterBankInfo::OperandsMapper::setVRegs(unsigned OpIdx, in setVRegs()
592 RegisterBankInfo::OperandsMapper::getVRegs(unsigned OpIdx, in getVRegs()
DRegBankSelect.cpp365 for (unsigned OpIdx = 0, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; in computeMapping() local
482 unsigned OpIdx = RepairPt.getOpIdx(); in applyMapping() local
568 MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P, in RepairingPlacement()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCodeEmitter.cpp922 unsigned OpIdx) { in getMachineSoRegOpValue()
1015 unsigned OpIdx = 0; in emitDataProcessingInstruction() local
1117 unsigned OpIdx = 0; in emitLoadStoreInstruction() local
1188 unsigned OpIdx = 0; in emitMiscLoadStoreInstruction() local
1273 unsigned OpIdx = 0; in emitLoadStoreMultipleInstruction() local
1316 unsigned OpIdx = 0; in emitMulFrmInstruction() local
1348 unsigned OpIdx = 0; in emitExtendInstruction() local
1391 unsigned OpIdx = 0; in emitMiscArithInstruction() local
1544 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { in encodeVFPRd()
1558 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { in encodeVFPRn()
[all …]
DARMExpandPseudoInsts.cpp419 unsigned OpIdx = 0; in ExpandVLD() local
483 unsigned OpIdx = 0; in ExpandVST() local
532 unsigned OpIdx = 0; in ExpandLaneOp() local
613 unsigned OpIdx = 0; in ExpandVTBL() local
977 unsigned OpIdx = 0; in ExpandMI() local
1007 unsigned OpIdx = 0; in ExpandMI() local
1038 unsigned OpIdx = 0; in ExpandMI() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DBreakFalseDeps.cpp108 bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx, in pickBestRegisterForUndef()
164 bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, in shouldBreakDependence()
220 unsigned OpIdx = UndefReads.back().second; in processUndefReads() local
DMachineInstr.cpp606 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, in findInlineAsmFlagIdx()
650 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint()
707 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC, in getRegClassConstraintEffectForVRegImpl()
719 unsigned OpIdx, const TargetRegisterClass *CurRC, in getRegClassConstraintEffect()
1234 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, in getTypeToPrint()
1298 auto getTiedOperandIdx = [&](unsigned OpIdx) { in print()
1364 const unsigned OpIdx = InlineAsm::MIOp_AsmString; in print() local
1607 unsigned OpIdx = DeadOps.back(); in addRegisterKilled() local
1671 unsigned OpIdx = DeadOps.back(); in addRegisterDead() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp112 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, in getRegBankFromConstraints()
179 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx; in getInstrMappingImpl() local
408 for (unsigned OpIdx = 0, in applyDefaultMapping() local
594 for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) { in print() local
614 RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) { in getVRegsMem()
650 void RegisterBankInfo::OperandsMapper::createVRegs(unsigned OpIdx) { in createVRegs()
670 void RegisterBankInfo::OperandsMapper::setVRegs(unsigned OpIdx, in setVRegs()
685 RegisterBankInfo::OperandsMapper::getVRegs(unsigned OpIdx, in getVRegs()
DInstructionSelector.cpp38 MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, in constrainOperandRegToRegClass()
DRegBankSelect.cpp414 for (unsigned OpIdx = 0, EndOpIdx = InstrMapping.getNumOperands(); in computeMapping() local
541 unsigned OpIdx = RepairPt.getOpIdx(); in applyMapping() local
657 MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P, in RepairingPlacement()
/external/swiftshader/third_party/LLVM/include/llvm/Analysis/
DConstantsScanner.h28 unsigned OpIdx; // Operand index variable
/external/llvm/lib/Target/AArch64/
DAArch64AddressTypePromotion.cpp208 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) { in shouldSExtOperand()
311 for (int OpIdx = 0, EndOpIdx = Inst->getNumOperands(); OpIdx != EndOpIdx; in propagateSignExtension() local
/external/llvm/utils/TableGen/
DCodeEmitterGen.cpp86 unsigned OpIdx; in AddCodeToMergeInOperand() local
192 unsigned OpIdx; in getInstructionCase() local
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeEmitterGen.cpp97 unsigned OpIdx; in AddCodeToMergeInOperand() local
200 unsigned OpIdx; in getInstructionCase() local
DGlobalISelEmitter.cpp1038 unsigned OpIdx; member in __anon0c06086d0111::PredicateMatcher
1041 PredicateMatcher(PredicateKind Kind, unsigned InsnVarID, unsigned OpIdx = ~0) in PredicateMatcher()
1083 unsigned OpIdx) in OperandPredicateMatcher()
1105 SameOperandMatcher(unsigned InsnVarID, unsigned OpIdx, StringRef MatchingName) in SameOperandMatcher()
1138 LLTOperandMatcher(unsigned InsnVarID, unsigned OpIdx, const LLTCodeGen &Ty) in LLTOperandMatcher()
1190 PointerToAnyOperandMatcher(unsigned InsnVarID, unsigned OpIdx, in PointerToAnyOperandMatcher()
1220 ComplexPatternOperandMatcher(unsigned InsnVarID, unsigned OpIdx, in ComplexPatternOperandMatcher()
1252 RegisterBankOperandMatcher(unsigned InsnVarID, unsigned OpIdx, in RegisterBankOperandMatcher()
1279 MBBOperandMatcher(unsigned InsnVarID, unsigned OpIdx) in MBBOperandMatcher()
1301 ConstantIntOperandMatcher(unsigned InsnVarID, unsigned OpIdx, int64_t Value) in ConstantIntOperandMatcher()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DProcessImplicitDefs.cpp49 unsigned Reg, unsigned OpIdx, in CanTurnIntoImplicitDef()
263 unsigned OpIdx = Ops[j]; in runOnMachineFunction() local
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp403 unsigned OpIdx = 0; in ExpandVLD() local
468 unsigned OpIdx = 0; in ExpandVST() local
522 unsigned OpIdx = 0; in ExpandLaneOp() local
605 unsigned OpIdx = 0; in ExpandVTBL() local
1383 unsigned OpIdx = 0; in ExpandMI() local
1414 unsigned OpIdx = 0; in ExpandMI() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp481 unsigned OpIdx = 0; in ExpandVLD() local
591 unsigned OpIdx = 0; in ExpandVST() local
667 unsigned OpIdx = 0; in ExpandLaneOp() local
750 unsigned OpIdx = 0; in ExpandVTBL() local
1577 unsigned OpIdx = 0; in ExpandMI() local
1608 unsigned OpIdx = 0; in ExpandMI() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h618 int OpIdx = MI.getOperandNo(&UseMO); in isInlineConstant() local
628 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const { in isInlineConstant()
633 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, in isInlineConstant()
660 bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const { in isLiteralConstant()
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenInstruction.cpp135 unsigned OpIdx; in getOperandNamed() local
171 unsigned OpIdx = getOperandNamed(OpName); in ParseOperandName() local

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