Searched defs:RegSeq (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1030 SDValue RegSeq = createQTuple(Regs); in SelectTable() local
1195 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore() local
1213 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore() local
1272 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane() local
1311 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane() local
1366 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane() local
1396 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1087 SDValue RegSeq = createQTuple(Regs); in SelectTable() local
1258 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore() local
1281 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore() local
1340 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane() local
1379 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane() local
1434 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane() local
1464 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1782 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST() local
2018 SDValue RegSeq; in SelectVTBL() local
3159 SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0); in Select() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 2061 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST() local
2304 SDValue RegSeq; in SelectVTBL() local
3709 SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0); in Select() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 1417 static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq, in HasOtherRegSequenceUses()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 2002 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST() local
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